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US 8,711,589 B2Granted
Direct converting apparatus, method for controlling the same, and control signal generation device
AssigneeDaikin Industries, Ltd.
InventorKenichi Sakakibara
Life of this patent
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Abstract
In a direct converting apparatus including a converter and a plurality of inverters, substantial carrier frequencies of the plurality of inverters are made different from each other while performing an operation in synchronization with the converter. An original carrier has a carrier frequency twice as high as a carrier frequency of a first carrier used for controlling one of the inverters. A waveform of the original carrier is magnified twice with a value serving as the center thereof, so that a second carrier used for controlling the other of the inverters is obtained.
Claims20
A method for controlling a direct converting apparatus,
- said direct converting apparatus comprising:
- a converter rectifying multi-phase AC voltages by a pulse-width modulation and outputting them to a pair of DC power supply lines;
- and
- a first inverter and a second inverter being connected in parallel with each other between said pair of DC power supply lines, each of them being operated in a pulse-width modulation according to an instantaneous space vector control,
- said method comprising:
- causing a commutation in said converter when a converter carrier takes the value of a converter command value, one cycle of said converter carrier being divided by a first value and a second value into a first time period and a second time period at a timing when said commutation is caused;
- adopting a zero vector in a first commutation zero vector time period which is a time period including said timing, as instantaneous space vectors adopted for said instantaneous space vector control of said first inverter;
- adopting a zero vector in a second commutation zero vector time period which is a time period including said timing, as instantaneous space vectors used for said instantaneous space vector control of said second inverter;
- in said first time period, adopting, M-times (M is an integer equal to or greater than 1), an arrangement pattern of said instantaneous space vectors in said first inverter except said zero vector adopted in said first commutation zero vector time period;
- and
- in said first time period, adopting, N-times (N is an integer equal to or greater than 2, and different from said M), an arrangement pattern of said instantaneous space vectors in said second inverter except said zero vector adopted in said second commutation zero vector time period.
8 more elements
A control signal generation device controlling a direct converting apparatus,
- said direct converting apparatus comprising:
- a converter rectifying multi-phase AC voltages and outputting them to a pair of DC power supply lines;
- and
- a first inverter and a second inverter being connected in parallel with each other between said pair of DC power supply lines,
- said control signal generation device comprising:
- a first inverter control section outputting a first control signal for operating said first inverter in a pulse-width modulation according to an instantaneous space vector control;
- a second inverter control section outputting a second control signal for operating said second inverter in a pulse-width modulation according to an instantaneous space vector control;
- and
- a converter control section outputting a third control signal for causing a commutation in said converter,
- said converter control section including:
- a carrier generation section generating a converter carrier;
- a converter command generation section generating a converter command value;
- a third control signal generation section generating said third control signal for performing a pulse-width control of said converter, by using a result of comparison between said converter carrier and said converter command value;
- and
- an intermediate phase detection section outputting a current conduction ratio of an intermediate phase of the command value for said converter,
- said first inverter control section including:
- a first output command generation section generating a first output command value which is a command value of an output of said first inverter;
- a first computation section generating a first inverter signal wave to be compared with a first carrier synchronized with said converter carrier, based on said current conduction ratio and said first output command value;
- and
- a first control signal generation section generating said first control signal based on a result of said comparison,
- said second inverter control section including:
- a second output command generation section generating a second output command value which is a command value of an output of said second inverter;
- a second computation section generating a second inverter signal wave to be compared with a second carrier synchronized with said converter carrier, based on said current conduction ratio and said second output command value;
- and
- a second control signal generation section generating said second control signal based on a result of said comparison,
- wherein
- as instantaneous space vectors adopted for said instantaneous space vector control of said first inverter, a zero vector is adopted in a first commutation zero vector time period which is a time period including a timing when said converter carrier takes the value of said intermediate phase,
- as instantaneous space vectors used for said instantaneous space vector control of said second inverter, a zero vector is adopted in a second commutation zero vector time period which is a time period including said timing,
- in one cycle of said converter carrier, in a first time period divided by said timing, an arrangement pattern of said instantaneous space vectors adopted by said first inverter except said zero vector adopted in said first commutation zero vector time period appears M-times (M is an integer equal to or greater than 1),
- in said first time period, an arrangement pattern of said instantaneous space vectors adopted by said second inverter except said zero vector adopted in said second commutation zero vector time period appears N-times (N is an integer equal to or greater than 2, and different from said M).
27 more elements
Dependencies are inferred from the claim text.