Gate timing for short servo wedge in disk memory systems

Abstract

The present disclosure describes systems and methods for controlling synchronization of a servo clock by tying the triggering of the gate signal of the position error signal field of the short servo wedge portion directly to the synchronization marker in the full servo wedge. The systems and methods described herein include controlling synchronization of a servo clock for reading servo information from a disk that is rotating relative to a read head. The systems and methods may include estimating a gate delay corresponding to a position error signal (PES) field in a short null servo wedge based, at least in part, on the location of the servo synchronization marker. The systems and methods include producing a servo clock timing control signal based on the estimated gate delay, and applying the servo clock timing control signal to the servo clock.

Dependencies are inferred from the claim text.