Storage device having clock adjustment circuitry with firmware-based predictive correction

A method comprising the steps of:

• obtaining a clock signal in a storage device comprising at least one storage disk;
• obtaining timing information by detecting a timing pattern on a surface of the storage disk;
• and
• generating a control signal for adjusting a parameter of the clock signal based at least in part on the timing information;
• wherein the control signal is generated utilizing a predictive correction control loop that is implemented at least in part using predictive control firmware, in combination with a reactive correction control loop that is implemented at least in part using reactive control hardware.

A processing system comprising:

• a processing device;
• and
• a storage device coupled to the processing device and comprising at least one storage disk;
• wherein the storage device further comprises:
• a read/write head configured to read data from and write data to the storage disk;
• and
• control circuitry coupled to the read/write head and configured to process data received from and supplied to the read/write head;
• the control circuitry comprising:
• clock adjustment circuitry configured to generate a control signal for adjusting a parameter of a clock signal based at least in part on timing information obtained by detecting a timing pattern on a surface of the storage disk;
• wherein the control signal is generated utilizing a predictive correction control loop in combination with a reactive correction control loop, the clock adjustment circuitry comprising predictive control firmware that implements at least a portion of the predictive correction control loop and reactive control hardware that implements at least a portion of the reactive correction control loop.

An apparatus comprising:

• at least one integrated circuit comprising control circuitry adapted for coupling to a read/write head configured to read data from and write data to a storage disk, the control circuitry being configured to process data received from and supplied to the read/write head;
• the control circuitry comprising:
• clock adjustment circuitry configured to generate a control signal for adjusting a parameter of a clock signal based at least in part on timing information obtained by detecting a timing pattern on a surface of the storage disk;
• wherein the control signal is generated utilizing at least a predictive correction control loop, the clock adjustment circuitry comprising predictive control firmware that implements at least a portion of the predictive correction control loop, wherein the clock adjustment circuitry further comprises a predictive correction module that is implemented outside of the predictive control firmware.

An apparatus comprising:

• at least one integrated circuit comprising control circuitry adapted for coupling to a read/write head configured to read data from and write data to a storage disk, the control circuitry being configured to process data received from and supplied to the read/write head;
• the control circuitry comprising:
• clock adjustment circuitry configured to generate a control signal for adjusting a parameter of a clock signal based at least in part on timing information obtained by detecting a timing pattern on a surface of the storage disk;
• wherein the control signal is generated utilizing at least a predictive correction control loop, the clock adjustment circuitry comprising predictive control firmware that implements at least a portion of the predictive correction control loop;
• and
• wherein the apparatus further comprises a processor and a memory coupled to the processor, the processor being configured to execute software code stored in the memory, wherein said software code when executed causes the clock adjustment circuitry to generate the control signal.