Solid-state image sensing device and control method of solid-state image sensing device

A solid-state sensing device, comprising:

• an image sensing region having pixels arranged in a two-dimensional array;
• a vertical shift register circuit that selects a desired pixel row of the pixels by changing the number of one or more clock signals supplied and timing thereof in one horizontal period;
• and
• a pulse selector circuit that supplies a drive pulse to the desired pixel row selected by the vertical shift register circuit, wherein
• the vertical shift register circuit includes
• first and second shift register circuits with the same circuit design that select a charge storage starting row of the pixels;
• and
• a third shift register circuit that selects a charge reading row in the pixels, and
• charges of pixels in rows of a number corresponding to the number of one or more clock signals input in an enable period of a control signal supplied to the third shift register circuit at a charge reading start timing are averaged.

A solid-state image sensing device comprising:

• an image sensing region having pixels arranged in a two-dimensional array, the pixels configuring pixel rows;
• a timing generator circuit that outputs one or more drive pulses to drive the pixels at common timing for each unit period and outputs one or more clock signals at common timing for each unit period, the timing generator circuit being configured to output the one or more clock signals of a variable number and timing in the unit period;
• a vertical shift register circuit that outputs a row select signal to select one of pixel rows determined by the number and timing of the one or more clock signals;
• and
• a pulse selector circuit that supplies the one or more drive pulses to the pixel row specified by the row select signal, wherein
• the one or more drive pulses include a pixel discharging drive pulse and pixel reading drive pulse,
• the one or more clock signals include a pixel discharging clock signal and a pixel reading clock signal,
• the row select signal includes a discharging row select signal to supply the pixel discharging drive pulse to a specified pixel row, and a reading row select signal to supply the pixel reading drive pulse to a specified pixel row,
• the vertical shift register circuit includes
• a first shift register circuit that outputs discharging row select signals so that one of the pixel rows is sequentially selected each time the pixel discharging clock signal is received;
• a second shift register circuit that has the same circuit design as the first shift register circuit, and outputs discharging row select signals so that one of the pixel rows is sequentially selected each time the pixel discharging clock signal is received;
• and
• a third shift register circuit that outputs reading row select signals so that one of the pixel rows is sequentially selected each time the reading clock signal is received, and
• the vertical shift register circuit is configured to output discharging row select signals to select different pixel rows in the same unit period.