Arbitration circuit to arbitrate conflict between read/write command and scan command and display driver integrated circuit having the same

An arbitration circuit usable with an electronic apparatus, comprising:

• a latch unit comprising a first latch circuit that latches and outputs a first signal related to a scan command and a second latch circuit that latches and outputs a second signal related to a read/write command, wherein the latch unit resets outputs of the first latch circuit and/or the second latch circuit in response to a ready signal related to a memory operation;
• and
• a maintaining unit to receive outputs of the first latch circuit and the second latch circuit, to generate a first internal signal to activate a scanning operation and a second internal signal to activate a reading/writing operation, to maintain the first internal signal and the second internal signal, and to selectively activate the first internal signal or the second internal signal by changing the state of at least one of the first internal signal and second internal signal in response to the reset operation,
• wherein the maintaining unit comprises:
• a first NAND operation unit to receive the output of the first latch circuit through a first input terminal thereof and performing a NAND operation;
• and
• a second NAND operation unit to receive the output of the second latch circuit through a first input terminal thereof, to receive the output of the first NAND operation unit through a second input terminal thereof, to perform a NAND operation, and to provide the output thereof to a second input terminal of the first NAND operation unit.

A driver integrated circuit usable with an electronic apparatus, comprising:

• a memory unit to store image data;
• a memory controller to control a scanning operation and reading/writing operation of the memory unit;
• and
• an arbitration circuit interposed between the memory unit and the memory controller to arbitrate a conflict between a scan command and a read/write command provided from the memory controller, to receive a ready signal comprising information related to an operation of the memory unit, to selectively activate and output a first internal signal to activate a scanning operation or a second internal signal to activate a reading/writing operation in response to the ready signal, the arbitration circuit having:
• a latch unit comprising a first latch circuit that latches and outputs a first signal related to a scan command and a second latch circuit that latches and outputs a second signal related to a read/write command, wherein the latch unit resets outputs of the first latch circuit and/or the second latch circuit in response to a ready signal related to a memory operation;
• a maintaining unit to receive outputs of the first latch circuit and the second latch circuit, to generate the first internal signal to activate the scanning operation and the second internal signal to activate the reading/writing operation, to maintain the first internal signal and the second internal signal, and to selectively activate the first internal signal or the second internal signal by changing the state of at least one of the first internal signal and second internal signal in response to the reset operation, an information signal generating unit to generate an information signal indicating a section of a scanning operation or a reading/writing operation of the memory in response to any one of the first internal signal and the second internal signal;
• a control signal generating unit to generate a control signal in which a clock is activated in correspondence to the activation of each of the first internal signal and the second internal signal and to control the scanning operation or the reading/writing operation of the memory to be performed;
• and
• a multiplexer to receive a scan address and a read/write address and to selectively output any one address in response to the information signal,
• wherein during a conflict of the first internal signal and the second internal signal, either signal, once activated, is maintained without interruption until completion of its respective operation.

An electronic apparatus comprising:

• a functional unit to perform a displaying operation to display an image on a screen thereof using data;
• and
• a driver integrated circuit to control the functional unit, and comprising:
• a memory unit to store the data;
• a memory controller to control a scanning operation and a reading/writing operation of the memory unit;
• and
• an arbitration unit interposed between the memory unit and the memory controller to arbitrate a conflict between a scan command and a read/write command provided from the memory controller, to receive a ready signal comprising information related to an operation of the memory unit, to selectively activate and output a first internal signal to activate a scanning operation or a second internal signal to activate a reading/writing operation in response to the ready signal, the arbitration circuit having:
• a latch unit comprising a first latch circuit that latches and outputs a first signal related to a scan command and a second latch circuit that latches and outputs a second signal related to a read/write command, wherein the latch unit resets outputs of the first latch circuit and/or the second latch circuit in response to a ready signal related to a memory operation;
• a maintaining unit to receive outputs of the first latch circuit and the second latch circuit, to generate the first internal signal to activate the scanning operation and the second internal signal to activate the reading/writing operation, to maintain the first internal signal and the second internal signal, and to selectively activate the first internal signal or the second internal signal by changing the state of at least one of the first internal signal and second internal signal in response to the reset operation,
• an information signal generating unit to generate an information signal indicating a section of a scanning operation or a reading/writing operation of the memory in response to any one of the first internal signal and the second internal signal;
• a control signal generating unit to generate a control signal in which a clock is activated in correspondence to the activation of each of the first internal signal and the second internal signal and to control the scanning operation or the reading/writing operation of the memory to be performed;
• and
• a multiplexer to receive a scan address and a read/write address and to selectively output any one address in response to the information signal,
• wherein during a conflict of the first internal signal and the second internal signal, either signal, once activated, is maintained without interruption until completion of its respective operation.

A non-transitory computer-readable medium having executable programming instructions stored thereon to perform a method of driving a driver IC unit usable with an electronic apparatus having a functional unit to display an image according to data, the method comprising:

• storing the data in a memory unit;
• and
• controlling the memory unit to scan the data of the memory unit in a scanning operation and to read/write the data in the memory unit in a read/write operation, processing a first signal to perform one of the scanning operation and the read/write operation on the memory unit, and delaying the processing of a second signal to perform the other one of the scanning operation
• and the read/write operation until the one of the scanning operation and the read/write operation has been finished according to the processed first signal regardless of which operation the first signal corresponds to.