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US 8,711,153 B2Granted
Methods and apparatuses for configuring and operating graphics processing units
AssigneeIntel Corporation
InventorsItay Franko, Anshuman Thakur
Life of this patent
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Abstract
A graphics processing system with multiple graphics processing cores (GPC)s is disclosed. The apparatus can include a peripheral component interface express (PCIe) switch to interface the GPCs to a host processor. The apparatus can also include a transparent bus to connect the GPCs. The transparent bus can be implemented with two PCIe endpoints on each side of a nontransparent bridge where these three components provide a bus interconnect and a control line interconnect between the GPCs. Other embodiments are also disclosed.
Claims19
An apparatus comprising:
- a first graphics processing core powered via a first power plane;
- a peripheral component interface switch coupled to the first graphics processing core to interface the first graphics processing core with a host via a peripheral component interface bus;
- a first peripheral component interface endpoint coupled to the first graphics processing core;
- and
- a second peripheral component interface endpoint coupled with the first peripheral component interface endpoint, the second peripheral component interface endpoint having an output to couple to a second graphics processing core powered via a second power plane, wherein a power interconnection between the second peripheral component interface endpoint and the second graphics processing core can transfer power of the second power plane to the second peripheral component interface endpoint, the power states of the second graphics processing core and the second peripheral component interface endpoint to be synchronized.
2 more elements
A system comprising:
- a first graphics processing core coupled with a processor via a first peripheral component interface switch;
- a second graphics processing core coupled with the processor via a second peripheral component interface switch;
- a first peripheral component interface endpoint coupled to the first graphics processing core;
- and
- a second peripheral component interface endpoint coupled to the first peripheral component interface endpoint and to the second graphics processing core, the first peripheral component interface endpoint to control a graphics bus between the first and second peripheral component interface endpoints and to transfer signals between the first graphics processing core and the second graphics processing core, wherein the first peripheral component interface endpoint is to receive a card reset signal from the second graphics processing core in response to transmission of the card reset signal from the processor to the second graphics processing core.
2 more elements
A method comprising:
- detecting a first graphics processing core;
- detecting a second graphics processing core;
- connecting the first graphics processing core to the second graphics processing core via a first peripheral component interface endpoint and a second peripheral component interface endpoint;
- and
- supplying power via a power interconnection between the second peripheral component interface endpoint and a power plane of the second graphics processing core, wherein power states of the second peripheral component interface endpoint and the second graphics processing core are synchronized.
2 more elements
Dependencies are inferred from the claim text.