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US 8,711,076 B2Granted
Timing controller capable of removing surge signal and display apparatus including the same
AssigneeSamsung Electronics Co., Ltd.
InventorsOck Chul Shin, Yeong Cheol Rhee, Byung Koan Kim
Life of this patent
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Abstract
A timing controller includes a first stage removing a first surge signal generated during a first logic level period of a data enable signal, and a second stage receiving the data enable signal generated by the first stage and removing a second surge signal generated during a second logic level period of the received data enable signal.
Claims19
A timing controller comprising:
- a first stage configured to remove a first surge signal during only a first logic level period of a data enable signal to generate a modified data enable signal;
- and
- a second stage configured to receive the modified data enable signal generated by the first stage and remove a second surge signal during only a second logic level period of the modified data enable signal,
- wherein the first logic level differs from the second logic level,
- wherein the data enable signal comprises a first data enable signal and a second data enable signal, and the timing controller further comprising a third stage that latches each of the first data enable signal and the second data enable signal based on a clock signal, performs a logic operation on the latched first and second enable signals, and outputs a logic operation result as a data enable signal input to the first stage.
2 more elements
A timing controller for driving a source driver and a gate driver of a display apparatus, the timing controller comprising:
- a timing controller configured to receive odd image data, even image data, an odd data enable signal, and an even data enable signal, output image data from the odd and even image data, and output a corrected data enable signal, the timing controller comprising:
- a first stage configured to latch the odd image data, even image data, odd data enable signal, and even data enable signal in response to a clock signal, perform a logical operation on the latched odd and even data enable signals to generate a first data enable signal, and output the image data from the odd and even image data;
- a second stage configured to receive the first data enable signal and the image data from the first stage and remove a first surge signal generated during a first logic level period of the first data enable signal to generate a second data enable signal;
- and
- a third stage configured to receive the second data enable signal and the image data from the second stage and remove a second surge signal generated during a second logic level period of the received data enable signal to generate the corrected data enable signal.
2 more elements
A display apparatus comprising:
- a timing controller configured to receive odd image data, even image data, odd data enable signal, and even data enable signal, output image data from the odd and even image data, output a corrected data enable signal from the odd and even data enable signals, and a gate control signal, the timing controller comprising:
- a low voltage differential signaling (LVDS) signal receiving unit configured to output odd image data, even image data, an odd data enable signal indicating an effective period of the odd image data, an even data enable signal indicating an effective period of the even image data, and a clock signal;
- a first stage configured to latch the odd image data, even image data, odd data enable signal, and even data enable signal in response to the clock signal, perform a logical operation on the latched odd and even data enable signals to generate a first data enable signal, and output the image data from the odd and even image data;
- a second stage configured to receive the first data enable signal and the image data from the first stage and remove a first surge signal generated during a first logic level period of the first data enable signal to generate a second data enable signal;
- and
- a third stage configured to receive the second data enable signal and the image data from the second stage and remove a second surge signal generated during a second and different logic level period of the received data enable signal to generate the corrected data enable signal;
- a display panel including data and gate lines;
- a source driver configured to receive the image data and the corrected data enable signal from the timing controller and drive the data lines of the display panel;
- and
- a gate driver configured to receive the gate control signal from the timing controller and drive the gate lines of the display panel.
7 more elements
Dependencies are inferred from the claim text.