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US 8,711,073 B2Granted
Flat panel crystal display employing simultaneous charging of main and subsidiary pixel electrodes
AssigneeSamsung Display Co., Ltd.
InventorsMin Cheol Lee, Seung Hwan Moon
Life of this patent
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Abstract
A display system includes a display panel having a plurality of pixel units, each of the pixel units having first and second divided pixel parts; a first driver for applying a first gate signal to the first divided pixel part; and a second driver for applying a second gate signal to the second divided pixel part, wherein the first and second drivers are integrally formed in the display panel and apply the first and second gate signals to be at least partially time-overlapped through independent driving.
Claims17
A display system, comprising:
- a display panel including a plurality of pixel units, where the pixel units are arranged as a matrix having respective rows of the pixel units, each of the pixel units having at least a main subpixel and one or more subsidiary subpixels,
- wherein the main and subsidiary subpixels of each pixel unit are coupled to receive respective charges from a same data line associated with the given pixel unit;
- a first driver for applying, by way of corresponding first gate lines, first gate signals to respective first thin film transistors used to charge and discharge the respective main subpixels;
- and
- a second driver for applying, by way of corresponding second gate lines, second gate signals to respective second thin film transistors used to charge and discharge the respective subsidiary subpixels,
- wherein the first and second drivers generate the respective first and second gate signals thereof independently such that the first and second gate signals can have partially time-overlapped turn-on levels,
- wherein each of the first and second drivers includes a respective plurality of sequentially connected shift register stages, the first driver having more shift register stages than the second driver,
- wherein
- the first driver comprises a first gate clocks generator for generating first and second main gate clock signals, said plurality of sequentially connected shift register stages of the first driver includes a plurality of first application timing circuits for timing application of turn-on levels of the first gate signals to the main subpixels in response to the first and second main gate clock signals, and
- the second driver comprises a second gate clocks generator for generating first and second subsidiary gate clock signals, said plurality of sequentially connected shift register stages of the second driver includes a plurality of second application timing circuits for timing application of turn-on levels of the second gate signals to the subsidiary subpixels in response to the first and second subsidiary gate clock signals, and
- wherein said plurality of sequentially connected shift register stages of the first driver further includes a plurality of reset timing circuits interposed between the first application timing circuits for defining a duration of turn-on drive time provided by the first application timing circuits relative to total time consumed by combination of the reset timing circuits and the first application timing circuits.
8 more elements
A method of controlling potentials charged onto divided pixel parts of respective pixel units in a display system, wherein the pixel units are arranged as a matrix having respective rows of the pixel units, wherein each divided pixel part has a corresponding electronic switch for applying a data line signal to the divided pixel part, and wherein the corresponding electronic switch is controlled by a corresponding gate line not the same as that of other divided pixel parts of the same pixel unit and not shorted to a gate line of another row of the matrix, the method comprising:
- dividing a horizontal line period (H) into a plurality of time segments;
- turning on the electronic switch of a first of the divided pixel parts of a given pixel unit for a first duration defined by one or more of the time segments by using the corresponding gate line and a first shift register, the first shift register having a first plural number of shift register stages;
- turning on the electronic switch of a second of the divided pixel parts of the given pixel unit for a second duration defined by a different one or more of the time segments where the second duration overlaps at least partially with the first duration by using the corresponding gate line and a second shift register which is driven independently of the first shift register, the second shift register having a second plural number of shift register stages different from that of the first shift register;
- applying a first voltage to a data line of the given pixel unit during the overlap time, the data line coupling to the electronic switches of the first and second divided pixel parts;
- and
- applying a second voltage, different from the first voltage, to the data line of the given pixel unit during a part of the horizontal line period (H) when the first and second durations do not overlap,
- wherein said second plural number of shift register stages of the second shift register includes dummy shift stages that do not cause the electronic switch of either a first or second of the divided pixel parts to turn on but instead defines a time of nonoverlap between the first and second durations.
4 more elements
A display system, comprising:
- a display panel including a plurality of pixel units, wherein the pixel units are arranged as a matrix having respective rows of the pixel units, each of the pixel units having at least a first divided pixel part and a second divided pixel part;
- a first driver for applying, by way of a corresponding first gate line, a first gate signal to the first divided pixel part, the first driver having a respective first plurality of shift register stages connected sequentially one to the next;
- and
- a second driver for applying, by way of a corresponding second gate line, a second gate signal to the second divided pixel part, the second driver having a respective second plurality of shift register stages connected sequentially one to the next,
- wherein the first and second drivers are configured so that an on time of the first gate signal is substantially equal to a predetermined horizontal line time of a corresponding display and an on time of the second gate signal is 1/(n+1) of the predetermined horizontal line time, where n is a whole number,
- wherein the second plurality of shift register stages of the second driver comprises a plurality of second application timing circuits for applying second gate signals to the second divided pixel parts and a plurality of reset timing circuits, and
- wherein each of the second application timing circuits alternates in said sequential connecting of the stages with a predefined whole number n of the reset timing circuits.
4 more elements
Dependencies are inferred from the claim text.