Data converter with configurable functions

A method for configurable data conversion, the method comprising:

• providing a data conversion array (DCA) with a plurality of selectively engageable data conversion circuits for conversion from analog input signals to digital output signals, wherein from data conversion circuits are selected from a group consisting of configurable data resolution circuits, configurable data conversion speed circuits, and both configurable data resolution and configurable data conversion speed circuits;
• the DCA receiving a configuration signal;
• in response to receiving the configuration signal, the DCA selecting a first data conversion circuit, which is a configurable data resolution circuit selected from a group consisting of averaging, oversampling, multi-stage pipelining, and combinations of the above-listed circuits;
• the DCA receiving analog input signals;
• the DCA processing the analog input signals using the first data conversion circuit, which is a configurable data resolution averaging circuit for parallelly sampling a first analog input signal a plurality of instances;
• the DCA supplying digital output signals as follows:
• supplying digital output signals with a first signal-to-noise ratio (SNR) in response to each analog input signal sample:
• averaging the digital output signals;
• and,
• supplying an averaged digital output signal with a second SNR, greater than the first SNR.

A data converter module comprising:

• an analog interface to receive analog input signals;
• a digital interface to transmit digital output signals;
• a configuration interface to accept configuration signals;
• a data conversion array (DCA) with a plurality of selectively engageable data conversion circuits for the conversion of the analog input signals to the digital output signals, where the data conversion circuits are responsive to the configuration signals;
• wherein the DCA selectively engageable data conversion circuits are chosen from a group consisting of configurable data resolution circuits, configurable data conversion speed circuits, and both configurable data resolution circuits and configurable data conversion speed circuits;
• wherein the DCA configurable data resolution circuits are selected from a group consisting of averaging, oversampling, multi-stage pipelining, and a combination of the above-mentioned circuits;
• and,
• wherein the DCA oversampling circuit comprises:
• an ADC having an analog input to accept an analog input signal having a first signal frequency, a digital output to supply a digital output signal having a first SNR, and a clock input for accepting a first clock signal having a first clock frequency greater than the first signal frequency, where the analog signal is sampled at the first clock frequency;
• and,
• a digital decimation filter having an input to accept the ADC digital output signal, a clock input for accepting a second clock signal having a second clock frequency, greater than or equal to the first signal frequency, and a digital output to supply an oversampled digital output signal having a second SNR, greater than the first SNR.

A data converter module comprising:

• an analog interface to receive analog input signals;
• a digital interface to transmit digital output signals;
• a configuration interface to accept configuration signals;
• and,
• a data conversion array (DCA) with a plurality of selectively engageable data conversion circuits for the conversion of the analog input signals to the digital output signals, where the data conversion circuits are responsive to the configuration signals;
• wherein the DCA selectively engageable data conversion circuits are chosen from a group consisting of configurable data resolution circuits, configurable data conversion speed circuits, and both configurable data resolution circuits and configurable data conversion speed circuits;
• wherein the DCA configurable data speed circuit comprises:
• a clock having a first plurality of clock outputs to supply a first clock signal at a first frequency with a first plurality of clock phases, each clock output being associated with a unique clock phase;
• a first plurality of ADCs, each ADC having an input to accept an analog input signal, a clock input to accept a corresponding first clock signal clock phase, and an output to supply a digital output signal at a first data rate in response to sampling the analog input signal at the first frequency;
• and,
• an interleaver having inputs connected to the first plurality of ADC digital outputs, and an output to supply an interleaved digital output signal having a second data rate, greater than the first data rate.

A method for configurable data conversion, the method comprising:

• providing a data conversion array (DCA) with a plurality of selectively engageable data conversion circuits for conversion from analog input signals to digital output signals, wherein from data conversion circuits are selected from a group consisting of configurable data resolution circuits, configurable data conversion speed circuits, and both configurable data resolution and configurable data conversion speed circuits;
• the DCA receiving a configuration signal;
• in response to receiving the configuration signal, the DCA selecting a first data conversion circuit, which is a configurable data resolution circuit selected from a group consisting of averaging, oversampling, multi-stage pipelining, and combinations of the above-listed circuits;
• the DCA receiving analog input signals;
• the DCA processing the analog input signals using the first data conversion circuit, which is a configurable data resolution oversampling circuit for sampling an analog input signal having a first signal frequency, at a first clock frequency, greater than the first signal frequency;
• the DCA supplying digital output signals as follows:
• supplying a digital output signal having a first SNR;
• sampling the digital output signal at a second clock frequency, greater than or equal to the first signal frequency;
• and,
• supplying an oversampled digital output signal having a second SNR, greater than the first SNR.

A method for configurable data conversion, the method comprising:

• providing a data conversion array (DCA) with a plurality of selectively engageable data conversion circuits for conversion from analog input signals to digital output signals, wherein from data conversion circuits are selected from a group consisting of configurable data resolution circuits, configurable data conversion speed circuits, and both configurable data resolution and configurable data conversion speed circuits;
• the DCA receiving a configuration signal;
• in response to receiving the configuration signal, the DCA selecting a first data conversion circuit;
• the DCA receiving analog input signals;
• the DCA processing the analog input signals using the first data conversion circuit, which is a configurable data speed circuit for sampling a first analog input signal using a first clock having a first frequency with a first plurality of clock phases;
• the DCA supplying digital output signals as follows:
• supplying a first plurality of digital output signals at a first data rate in response to sampling the first analog input signal;
• interleaving the first plurality of digital output signals;
• and,
• supplying an interleaved digital output signal having a second data rate, greater than the first data rate.