Switched capacitor amplifier

#This application is a U.S. National Stage patent application based on PCT Application Number PCT/EP2009/057734, filed on Jun. 22, 2009, entitled “Switched Capacitor Amplifier”, which application claims the priority benefit of European patent application number 08305375.1, filed on Jul. 3, 2008, entitled “Switched Capacitor Amplifier,” which applications are hereby incorporated by reference to the maximum extent allowable by law.

#1. Field of the Invention

#The present invention relates to a switched capacitor amplifier, and in particular to a switched capacitor amplifier having two phases of operation.

#The foregoing and other purposes, features, aspects and advantages of the invention will become apparent from the following detailed description of embodiments, given by way of illustration and not limitation with reference to the accompanying drawings, in which:

#FIG. 1 illustrates a switched capacitor amplifier according to an embodiment of the present invention;

#FIG. 2 illustrates a switched capacitor amplifier according to a further embodiment of the present invention;

#FIG. 1 illustrates a switched capacitor amplifier 100. As illustrated, amplifier 100 comprises an amplification unit 102, having differential positive and negative inputs 104 and 106 respectively, and differential negative and positive outputs 108 and 110 respectively. In particular, the amplification unit is arranged to be driven by one differential input signal at a time, and thus comprises a single pair of differential inputs and outputs. The amplifier circuit comprises a pair of differential input terminals 112 and 114, and a pair of differential input terminals 116 and 118. Input terminals 112 to 118 receive input voltage signals VINP1, VINN1, VINP2 and VINN2 respectively.

#Input terminals 112 and 114 are coupled to the inputs of a switched capacitor block 120, which comprises a number of switched capacitors (not shown in FIG. 1). Input terminals 116 and 118 are coupled to the input nodes of a switched capacitor block 122, which also comprises a number of switched capacitors (not shown in FIG. 1). The switched capacitor blocks 120 and 122 each comprise differential outputs coupled to a switch block 124. Switch blocks 120, 122 and 124 are controlled by timing signals Ø1 and Ø2. These timing signals select when the differential outputs of the switch capacitor block 120 or the differential outputs from the switched capacitor block 122 are coupled the differential input terminals 104 and 106 of the differential amplification unit. The timing signals Ø1 and Ø2 are, for example, generated by control circuitry (not shown in FIG. 1).

#The output terminals 108 and 110 of the amplification unit 102 provide differential output signals VOUTP and VOUTN of the circuit. VOUTP has opposite phase to input signal EN of the amplification unit, while VOUTP has opposite phase to input signal EP of the amplification unit. These signals are also provided to a feedback control block 128, which is coupled to outputs 108 and 110 and generates a control signal based on these signals to a comparator 130 of the amplification unit 102. This control signal provides common mode feedback, allowing the common mode of the output signals to be controlled.