Providing a feedback loop in a low latency serial interconnect architecture
AssigneeIntel Corporation
InventorsEhud Shoor, Dror Lazar, Assaf Benhamou
Life of this patent
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Abstract
In one embodiment, the present invention includes a de-serializer to receive serial data at a first rate and to output a parallel data frame corresponding to the serial data aligned to a frame alignment boundary in response to a phase control signal received from a feedback loop coupled between the de-serializer and a receiver logic coupled to an output of the de-serializer. Other embodiments are described and claimed.
Claims19
An apparatus comprising:
- an analog front end including:
- a receiver front end to receive and condition an analog signal into serial data;
- and
- a de-serializer to receive the serial data at a first rate and to output a parallel data frame corresponding to the serial data and having a bit width of N, wherein the de-serializer is to output the parallel data frame aligned to a frame alignment boundary in response to a phase control signal;
- and
- a receiver logic including digital logic coupled to the de-serializer to receive the parallel data frame from the de-serializer, wherein the receiver logic is to feedback the phase control signal to the de-serializer, the digital logic to not perform frame alignment on the parallel data frame.
A non-transitory machine-readable medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:
- receiving serial data in a de-serializer of a receiver;
- converting the serial data to parallel data and providing the parallel data unaligned to a frame boundary from the de-serializer to a digital logic of the receiver;
- receiving a load strobe signal in the de-serializer from the digital logic based on determination of the frame boundary in the digital logic;
- and
- thereafter providing the parallel data from the de-serializer to the digital logic that is aligned to the frame boundary responsive to the load strobe signal.
A system comprising:
- a transmitter to transmit serial data to a receiver via a link, the transmitter including:
- a transmit logic to receive incoming data from a logic unit of the transmitter and to convert the incoming data into parallel data at a first rate;
- a serializer to receive the parallel data and to generate a serial bit stream at a second rate;
- and
- a driver to drive the serial bit stream on the link as the serial data;
- and
- the receiver to receive the serial data and including:
- a receiver front end to receive and condition the serial data;
- a de-serializer to receive the serial data and to output therefrom a parallel data frame aligned to a frame alignment boundary in response to a phase control signal;
- and
- a receiver logic coupled to the de-serializer to receive the parallel data frame from the de-serializer, wherein the receiver logic is to feedback the phase control signal to the de-serializer.
Dependencies are inferred from the claim text.