Serial transmission system including transmitter apparatus and receiver apparatus, for use in transmission of AV data

A transmitter apparatus for converting parallel data of natural number p units, whose one unit is parallel data of natural number n multiplied by 12 bits, into (n multiplied by p) pieces of serial data, and transmitting n transmission signals each of natural number m bits, the transmitter apparatus comprising:

• dividing buffer configured to divide inputted parallel data into (n multiplied by p) pieces of 12-bit parallel data;
• an encoder circuit configured to 12B14B-convert the (n multiplied by p) pieces of 12-bit parallel data into (n multiplied by p) pieces of 14-bit parallel data, respectively, and output resulting data;
• a parallel-to-serial converter circuit configured to parallel-to-serial convert the (n multiplied by p) pieces of 14-bit parallel data into (n multiplied by p) pieces of 1-bit serial data, and output resulting data;
• and
• an m-bit driver circuit configured to amplify and transmit the (n multiplied by p) pieces of 1-bit serial data, as n transmission signals each of m bits, respectively, to q transmission paths, where q is a minimum natural number equal to or larger than (n multiplied by p)/m.

A receiver apparatus for receiving natural number n transmission signals each of natural number m bits, and converting n pieces of serial data into n pieces of parallel data, respectively, the receiver apparatus comprising:

• an m-bit receiver circuit configured to receive n transmission signals each of natural number m bits from n transmission paths, and generate n pieces of 1-bit serial data, respectively;
• a serial-to-parallel converter circuit configured to serial-to-parallel convert the n pieces of 1-bit serial data into n pieces of 14-bit parallel data, respectively, and generate a clock signal for synchronization from at least one piece of the n pieces of 1-bit serial data;
• and
• a decoder circuit configured to 14B12B-convert the n pieces of 14-bit parallel data into n pieces of 12-bit parallel data, respectively, by using the clock signal for synchronization, and output resulting data.

A receiver apparatus for receiving (n multiplied by p) transmission signals each of natural number m bits, and converting (n multiplied by p) pieces of serial data into (n multiplied by p) pieces of 12-bit parallel data, where n and p are natural numbers, the receiver apparatus comprising:

• an m-bit receiver circuit configured to receive (n multiplied by p) transmission signals each of natural number m bits from (n multiplied by p) transmission paths, respectively, and generate (n multiplied by p) pieces of 1-bit serial data;
• a serial-to-parallel converter circuit configured to serial-to-parallel convert the (n multiplied by p) pieces of 1-bit serial data into (n multiplied by p) pieces of 14-bit parallel data, respectively, and generate a clock signal for synchronization from at least one of the (n multiplied by p) pieces of 1-bit serial data;
• and
• a decoder circuit configured to 14B12B-convert the (n multiplied by p) pieces of 14-bit parallel data into (n multiplied by p) pieces of 12-bit parallel data by using the clock signal for synchronization, and output resulting data.

A serial transmission system comprising a transmitter apparatus and a receiver apparatus,

• wherein the transmitter apparatus is configured to convert parallel data of natural number n multiplied by 12 bits into n pieces of serial data, and transmit n transmission signals each of natural number m bits,
• wherein the transmitter apparatus comprises:
• a dividing buffer configured to divide inputted parallel data into n pieces of 12-bit parallel data;
• an encoder circuit configured to 12B14B-convert the n pieces of 12-bit parallel data into n pieces of 14-bit parallel data, respectively, and output resulting data;
• a parallel-to-serial converter circuit configured to parallel-to-serial convert the n pieces of 14-bit parallel data into n pieces of 1-bit serial data, respectively, and output resulting data;
• and
• an m-bit driver circuit configured to amplify and transmit the n pieces of 1-bit serial data, as n transmission signals each of m bits, respectively, to n transmission paths,
• wherein the receiver apparatus configured to receive natural number n transmission signals each of natural number m bits, and convert n pieces of serial data into n pieces of parallel data, respectively,
• wherein the receiver apparatus comprises:
• an m-bit receiver circuit configured to receive n transmission signals each of natural number m bits from n transmission paths, and generate n pieces of 1-bit serial data, respectively;
• a serial-to-parallel converter circuit configured to serial-to-parallel convert the n pieces of 1-bit serial data into n pieces of 14-bit parallel data, respectively, and generate a clock signal for synchronization from at least one piece of the n pieces of 1-bit serial data;
• and
• a decoder circuit configured to 14B12B-convert the n pieces of 14-bit parallel data into n pieces of 12-bit parallel data, respectively, by using the clock signal for synchronization, and output resulting data.

A serial transmission system comprising a transmitter apparatus and a receiver apparatus,

• wherein the transmitter apparatus is configured to convert parallel data of natural number p units, whose one unit is parallel data of natural number n multiplied by 12 bits, into (n multiplied by p) pieces of serial data, and transmit n transmission signals each of natural number m bits,
• wherein the transmitter apparatus comprises:
• dividing buffer configured to divide inputted parallel data into (n multiplied by p) pieces of 12-bit parallel data;
• an encoder circuit configured to 12B14B-convert the (n multiplied by p) pieces of 12-bit parallel data into (n multiplied by p) pieces of 14-bit parallel data, respectively, and output resulting data;
• a parallel-to-serial converter circuit configured to parallel-to-serial convert the (n multiplied by p) pieces of 14-bit parallel data into (n multiplied by p) pieces of 1-bit serial data, and output resulting data;
• and
• an m-bit driver circuit configured to amplify and transmit the (n multiplied by p) pieces of 1-bit serial data, as n transmission signals each of m bits, respectively, to q transmission paths, where q is a minimum natural number equal to or larger than (n multiplied by p)/m,
• wherein the receiver apparatus is configured to receive (n multiplied by p) transmission signals each of natural number m bits, and convert (n multiplied by p) pieces of serial data into (n multiplied by p) pieces of 12-bit parallel data, where n and p are natural numbers,
• wherein the receiver apparatus comprises:
• an m-bit receiver circuit configured to receive (n multiplied by p) transmission signals each of natural number m bits from (n multiplied by p) transmission paths, respectively, and generate (n multiplied by p) pieces of 1-bit serial data;
• a serial-to-parallel converter circuit configured to serial-to-parallel convert the (n multiplied by p) pieces of 1-bit serial data into (n multiplied by p) pieces of 14-bit parallel data, respectively, and generate a clock signal for synchronization from at least one of the (n multiplied by p) pieces of 1-bit serial data;
• and
• a decoder circuit configured to 14B12B-convert the (n multiplied by p) pieces of 14-bit parallel data into (n multiplied by p) pieces of 12-bit parallel data by using the clock signal for synchronization, and output resulting data.