Binary-to-gray converting circuits and gray code counter including the same
AssigneeSamsung Electronics Co., Ltd.
InventorsKyung-Min Kim, Jin-Woo Kim, Hee-Sung Chae
Life of this patent
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Abstract
A binary-to-Gray converting circuit includes a buffer unit and a conversion unit. The buffer unit generates a data code of n bits in response to a power supply voltage and a second binary bit signal through an nth binary bit signal except for a first binary bit signal corresponding to a least significant bit of a binary code of n bits. The conversion unit generates a Gray code of n bits based on the binary code and the data code, and generates a kth Gray bit signal of the Gray code by latching a kth data bit signal of the data code in response to a kth binary bit signal of the binary code. A logic level of the kth Gray bit signal is determined corresponding to a logic level of the kth data bit signal.
Claims20
A binary-to-Gray converting circuit, comprising:
- a buffer unit configured to generate a data code of n bits, where n is a natural number equal to or greater than two, in response to a power supply voltage and a second binary bit signal through an nth binary bit signal except for a first binary bit signal, the first binary bit signal corresponding to a least significant bit of a binary code of n bits, the second through nth binary bit signals corresponding to other bits of the binary code;
- and
- a conversion unit configured to generate a Gray code of n bits based on the binary code and the data code, and configured to generate a kth Gray bit signal, where k is a natural number equal to or greater than one and equal to or less than n, by latching a kth data bit signal in response to a kth binary bit signal, a logic level of the kth Gray bit signal being determined corresponding to a logic level of the kth data bit signal, the kth Gray bit signal corresponding to a kth bit of the Gray code, the kth data bit signal corresponding to a kth bit of the data code, and the kth binary bit signal corresponding to a kth bit of the binary code.
A Gray code counter, comprising:
- a binary counter circuit configured to generate a binary code of n bits, where n is a natural number equal to or greater than two, based on a power supply voltage and a clock signal;
- and
- a binary-to-Gray converting circuit configured to generate a Gray code of n bits based on the binary code and the power supply voltage,
- wherein the binary-to-Gray converting circuit comprises:
- a buffer unit configured to generate a data code of n bits in response to the power supply voltage and a second binary bit signal to an nth binary bit signal except for a first binary bit signal, the first binary bit signal corresponding to a least significant bit of the binary code, the second through nth binary bit signals corresponding to other bits of the binary code, the first through nth binary bit signals being sequentially toggled;
- and
- a conversion unit configured to generate the Gray code based on the binary code and the data code, and configured to generate a kth Gray bit signal, where k is a natural number equal to or greater than one and equal to or less than n, by latching a kth data bit signal in response to a kth binary bit signal of the binary code, a logic level of the kth Gray bit signal being determined corresponding to a logic level of the kth data bit signal, the kth Gray bit signal corresponding to a kth bit of the Gray code, the kth data bit signal corresponding to a kth bit of the data code, and the kth binary bit signal corresponding to a kth bit of the binary code.
A binary-to-Gray converting circuit, comprising:
- a buffer unit configured output a clock signal and a data signal, both based on a bit included in a binary code to be translated to a Gray code by the binary-to-Gray converting circuit;
- and
- a conversion unit, coupled to the buffer unit, configured to receive the clock signal at a clock input terminal of an upper stage of the conversion unit and configured to receive the data signal at a data input terminal of a lower stage of the conversion unit, relative to the upper stage.
Dependencies are inferred from the claim text.