MOS resistor apparatus and methods
AssigneeTexas Instruments Incorporated
InventorArup Polley
Life of this patent
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Abstract
Apparatus and methods disclosed herein implement a MOS resistor using the current channel of a MOS transistor. The MOS resistance R(DS) is dependent upon MOS transistor geometry and nominal gate voltage. MOS resistor terminal-to-gate voltages are averaged and applied to the MOS transistor gate such as to maintain the MOS resistor terminal voltage to current ratio, resulting in a substantially constant R(DS). R(DS) is also compensated for temperature and process variations by adjusting gate voltages via negative feedback methods.
Claims17
A metal oxide semiconductor (MOS) resistor, comprising:
- a MOS transistor with a gate terminal;
- two MOS resistor terminals, one associated with the MOS transistor source and one associated with the MOS transistor drain;
- first and second compensation resistors coupled to the MOS transistor gate terminal;
- a first gate voltage bias source communicatively coupled between a first one of the MOS resistor terminals and the first compensation resistor;
- and
- a second gate voltage bias source communicatively coupled between a second one of the MOS resistor terminals and the second compensation resistor,
- the first gate voltage bias source further comprising:
- a first reference current source;
- and
- a first forward-biased diode communicatively coupled between the first reference current source and the first MOS resistor terminal.
A metal oxide semiconductor (MOS) resistor, comprising:
- a cascaded plurality of MOS transistors, each MOS transistor coupled drain-to-source to the other MOS transistors of the cascaded plurality;
- an inter-gate compensation resistor coupled between a gate terminal of each MOS transistor and a gate terminal of a next MOS transistor in the cascaded plurality;
- two outermost compensation resistors, one outermost compensation resistor coupled to a gate terminal associated with each one of an outermost MOS transistor in the cascaded plurality;
- and
- two gate voltage bias sources, each gate voltage bias source communicatively coupled between a terminal of the MOS resistor and a most proximate one of the outermost compensation resistors,
- an absolute reference current source to provide a reference current I(ABS) substantially invariant with temperature;
- a first current mirror coupled to the absolute reference current source to factor I(ABS) by a factor X;
- a temperature proportional reference current source to provide a reference current I(TP) linearly proportional to an operating temperature associated with the MOS resistor;
- a second current mirror coupled to the temperature proportional reference current source to factor I(TP) by a factor (1−X);
- and
- a summing junction coupled to the first and second current mirrors to combine the factored I(ABS) and the factored I(TP) to obtain a bias reference current I(REF).
A method of maintaining a substantially constant ratio of terminal voltage to current through a metal oxide semiconductor (MOS) resistor formed by at least one MOS transistor drain-to-source channel, comprising:
- averaging gate-to-terminal voltages associated with each terminal of the MOS resistor to obtain an average gate voltage for the MOS transistor(s);
- and
- applying the average gate voltage to the gate(s) of the MOS transistor(s),
- passing a reference current I(REF) through a diode to obtain a diode voltage V(DI);
- adding V(DI) to a first MOS resistor terminal voltage to obtain a first preliminary bias voltage V(PB1);
- adding V(DI) to a second MOS resistor terminal voltage to obtain a second preliminary bias voltage V(PB2);
- and
- averaging V(PB1) and V(PB2) to obtain a MOS resistor gate voltage resulting in a constant ratio of MOS resistor terminal voltage to MOS resistor current.
Dependencies are inferred from the claim text.