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US 8,710,891 B2Granted
Semiconductor IC including pulse generation logic circuit
AssigneeSamsung Electronics Co., Ltd.
InventorHoi Jin Lee
Life of this patent
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Abstract
A pulse generation circuit includes storage elements disposed in a dispersed arrangement on a substrate and operating in response to a pulse signal, delay elements each proximate to a storage element receiving a clock signal and providing a delayed output signal, and a pulse generation logic circuit performing at least one logic operation on the clock signal and the plurality of delayed output signals to generate the pulse signal.
Claims20
A pulse generation circuit for a semiconductor integrated circuit (IC), the pulse generation circuit comprising:
- a plurality of storage elements disposed in a dispersed arrangement on a substrate, wherein each storage element in the plurality of storage elements operates in response to a same pulse signal;
- a plurality of delay elements, wherein the plurality of delay elements are respectively located adjacent to different ones of the plurality of storage elements such that the plurality of delay elements are similarly disposed in the dispersed arrangement on the substrate, and wherein each delay element receives a clock signal and provides a delayed output signal;
- and
- a pulse generation logic circuit that receives the clock signal and the delayed output signal from each of the plurality of delay elements, and performs at least one logic operation on the clock signal and each received delayed output signal to generate the same pulse signal.
1 more element
A data processing apparatus comprising:
- a data source;
- and
- a semiconductor integrated circuit (IC) that processes data provided by the data source, wherein the semiconductor IC includes a pulse generation circuit, comprising:
- a plurality of storage elements disposed in a dispersed arrangement on a substrate, wherein each storage element in the plurality of storage elements operates in response to a same pulse signal;
- a plurality of delay elements, wherein the plurality of delay elements are respectively located adjacent to different ones of the plurality of storage elements such that the plurality of delay elements are similarly disposed in the dispersed arrangement on the substrate, and wherein each delay element receives a clock signal and provides a delayed output signal;
- and
- a pulse generation logic circuit that receives the clock signal and the delayed output signal from each of the plurality of delay elements, and performs at least one logic operation on the clock signal and each received delayed output signal to generate the same pulse signal.
4 more elements
A semiconductor integrated circuit (IC), comprising:
- a clock tree including a plurality of tree branches that distribute a clock signal and a plurality of pulse distribution networks, wherein at least one of the pulse distribution networks includes a pulse generation circuit, wherein the pulse generation circuit comprises:
- a plurality of storage elements disposed in a dispersed arrangement on a substrate, wherein each storage element in the plurality of storage elements operates in response to a same pulse signal;
- a plurality of delay elements, wherein the plurality of delay elements are respectively located adjacent to different ones of the plurality of storage elements such that the plurality of delay elements are similarly disposed in the dispersed arrangement on the substrate, and wherein each delay element receives a clock signal and provides a delayed output signal;
- and
- a pulse generation logic circuit that receives the clock signal and the delayed output signal from each of the plurality of delay elements, and performs at least one logic operation on the clock signal and each received delayed output signal to generate the same pulse signal.
2 more elements
Dependencies are inferred from the claim text.