Delay lines, amplifier systems, transconductance compensating systems and methods of compensating

A delay line, comprising:

• a compensating circuit having at least one transistor and being configured to provide a bias signal at an output node having a magnitude that is a function of transconductance of the at least one transistor in the compensating circuit, the compensating circuit further comprising first and second input transistors having respective sources coupled to each other, respective drains coupled to the first supply voltage node through respective loads, and respective gates, the gate of the first input transistor being coupled to the drain of the second input transistor, and the gate of the second input transistor being coupled to the drain of the first input transistor;
• a current sink transistor having a drain coupled to the sources of the first and second input transistors, a source coupled to the second supply voltage node, and a gate coupled to the output node of the compensating circuit;
• and
• a comparison circuit configured to compare a reference voltage with a voltage corresponding to a difference in the magnitude of a first voltage at the drain of the first input transistor and a second voltage at the drain of the second input transistor, the comparison circuit being configured to provide the bias signal as a function of the comparison and to provide the bias signal to the output node of the compensating circuit;
• and
• a plurality of delay stages coupled to each other in series from a first delay stage to a last delay stage, each of the delay stages including at least one input transistor and being coupled to the output node of the compensating circuit, and each of the delay stages being configured to use the bias signal provided at the output node to maintain the gain of the respective delay stage substantially constant as a transconductance of the at least one input transistor in the respective delay stage changes, the delay stages further comprising first and second input transistors having respective sources coupled to each other, respective drains coupled to a first supply voltage node through respective loads, and respective gates coupled to receive respective differential input signal nodes, and a current sink coupling the sources of the first and second input transistors to a second supply voltage node, wherein the current sink comprises a current sink transistor having a drain coupled to the sources of the first and second input transistors, a source coupled to the second supply voltage node, and a gate coupled to the output node of the compensating circuit.

A delay line, comprising:

• a compensating circuit having at least one transistor and being configured to provide a bias signal at an output node having a magnitude that is a function of a transconductance of the at least one transistor in the compensating circuit;
• a plurality of delay stages coupled to each other in series from a first delay stage to a last delay stage, each of the delay stages including at least one input transistor and being coupled to the output node of the compensating circuit, and each of the delay stages being configured to use the bias signal provided at the output node to maintain the gain of the respective delay stage substantially constant as a transconductance of the at least one input transistor in the respective delay stage changes;
• and
• a start circuit configured to initially provide an input signal to the compensating circuit.

A delay line comprising:

• a plurality of delay stages coupled to each other in series from a first delay stage to a last delay stage, each of the delay stages including at least one input transistor, wherein the first and second transistors further have respective second source/drains coupled to a supply voltage through respective loads, and configured to receive a control signal, and each of the delay stages configured to provide a gain of the respective delay stage in accordance with the control signal;
• and
• a compensating circuit configured to generate the control signal, wherein the compensating circuit comprises a bias voltage generator having at least one transistor having same electrical characteristics as the at least one input transistor, wherein the at least one transistor of the bias voltage generator comprises a first and second transistor, each having the same electrical characteristics as the at least one input transistor, and wherein the first and second transistors have respective first source/drains coupled to each other, and wherein the control signal has a magnitude that is a function of a transconductance of the at least one transistor in the compensating circuit, wherein the compensating circuit further comprises a differential-to-single converter, the differential-to-single converter having inputs coupled to the second source/drains and the differential-to-single converter configured to convert a differential signal received at the inputs to a single-ended signal at an output.