US 8,710,869 B2Granted

High-speed comparator with asymmetric frequency response

AssigneeIntel Corporation

InventorsPeter Hazucha, Tsung-Hao Chen, Tanay Karnik, Chung-Ping Chen

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Abstract

A comparator to provide an output voltage indicative of comparing an input voltage with a reference voltage, where the comparator has an asymmetric frequency response. With an asymmetric frequency response, the bandwidth of the input voltage may be greater than the bandwidth of the reference voltage. A comparator includes a differential pair of transistors coupled to a current mirror and biased by a current source, where in one embodiment, a capacitor shunts the sources of the differential pair. In a second embodiment, a capacitor couples the input voltage port to the gates of the current mirror transistors. In a third embodiment, the comparator utilizes both capacitors of the first and second embodiments.

Claims11

Dependent claims

A die comprising a comparator, the comparator comprising:

a first transistor comprising a drain, a source, and a gate;
a second transistor comprising a drain, a source, and a gate;
a first input port connected to the gate of the first transistor;
a second input port connected to the gate of the second transistor;
an output port having an output voltage and connected to the drain of the second transistor;
a current mirror coupled to the first and second transistors;
a current source connected to the sources of the first and second transistors;
a first capacitor connected to the source of the second transistor,
the current mirror comprising:
a third transistor comprising a gate, a source, and a drain connected to the drain of the first transistor and connected to the gate of the third transistor;
a fourth transistor comprising a gate connected to the gate of the third transistor, a source connected to the source of the third transistor, and a drain connected to the drain of the second transistor;
and
a second capacitor comprising a first terminal connected to the gate of the second transistor, and comprising a second terminal connected to the gates of the third and fourth transistors.

10 more elements

A computer system comprising:

a die comprising a microprocessor;
an off-die memory coupled to the microprocessor;
a comparator comprising:
a first transistor comprising a drain, a source, and a gate;
a second transistor comprising a drain, a source, and a gate;
a first input port connected to the gate of the first transistor;
a second input port connected to the gate of the second transistor;
an output port having an output voltage and connected to the drain of the second transistor;
a current mirror coupled to the first and second transistors;
a current source connected to the sources of the first and second transistors;
a first capacitor connected to the source of the second transistor, wherein the first capacitor is chosen so as to reduce the trans-conductance of the comparator and avoid overshoot;
a utilization circuit coupled to the output port to latch the output voltage:
a voltage reference source to provide a reference voltage to the first input port a rail;
wherein the first capacitor comprises a first terminal connected to the source of the second transistor and a second terminal connected to the rail;
and
a second capacitor, the second capacitor comprises a first terminal connected to the gate of the second transistor, and comprises a second terminal connected to the gates of the third and fourth transistors.

13 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/422,238Filed 23 Apr 2003
Published: US 2011/0095788 A128 Apr 2011
Granted: 29 Apr 2014
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

H03K 5/2481
Using field effect transistors: with at least one differential stage
H03F 3/45183
Using MOSFET transistors as the active amplifying circuit: long tailed pairs
H03F 2203/45544
Indexing scheme relating to differential amplifiers: the IC comprising one or more capacitors, e.g. coupling capacitors
H03F 2203/45646
Indexing scheme relating to differential amplifiers: the LC comprising an extra current source