Sense-amplifier monotizer

A method of latching an input signal, the method comprising:

• outputting a select logic state while a clock signal is in a first phase;
• and
• sampling with an amplifier circuit a data signal and outputting at least one of the data signal and a complementary logic state of the data signal while the clock signal is in a second phase,
• wherein the amplifier circuit is latched responsive to a state transitioning of an output of the amplifier circuit as the data signal is sampled by the amplifier circuit while the clock signal is in the second phase and a logic state of the sampled data signal is kept by a keeper circuit once the data signal is sampled while the clock signal is in the second phase;
• wherein the amplifier circuit comprises two amplifier legs for sampling the data signal and a complementary logic state of the data signal, respectively, and the amplifier circuit is latched as the data signal and the complementary logic state of the data signal are sampled while the clock signal is in the second phase and wherein the data signal and the complementary logic state of the data signal drive a NAND gate which drives along with the clock signal a NOR gate, which drives a transistor of the amplifier legs, such that the amplifier circuit is latched as the data signal and the complementary logic state of the data signal are sampled while the clock signal is in the second phase.

A computer-readable storage medium storing a code for describing a structure and/or a behavior of an amplifier circuit for outputting a select logic state while a clock signal is in a first phase, and sampling a data signal and outputting at least one of the data signal and a complementary logic state of the data signal while the clock signal is in a second phase, wherein the amplifier circuit is latched responsive to a state transitioning of an output of the amplifier circuit as the data signal is sampled by the amplifier circuit while the clock signal is in the second phase and a logic state of the sampled data signal is kept by a keeper circuit once the data signal is sampled while the clock signal is in the second phase;

• wherein the amplifier circuit comprises two amplifier legs for sampling the data signal and a complementary logic state of the data signal, respectively, and the amplifier circuit is latched as the data signal and the complementary logic state of the data signal are sampled while the clock signal is in the second phase and wherein the data signal and the complementary logic state of the data signal drive a NAND gate which drives along with the clock signal a NOR gate, which drives a transistor of the amplifier legs, such that the amplifier circuit is latched as the data signal and the complementary logic state of the data signal are sampled while the clock signal is in the second phase.