Dynamically reconfigurable systolic array accelorators
AssigneeUtah State University
InventorsAravind Dasu, Robert C. Barnes
Life of this patent
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Abstract
A polymorphic systolic array framework that works in conjunction with an embedded microprocessor on an FPGA, that allows for dynamic and complimentary scaling of acceleration levels of two algorithms active concurrently on the FPGA. Use is made of systolic arrays and hardware-software co-design to obtain an efficient multi-application acceleration system. The flexible and simple framework allows hosting of a broader range of algorithms and extendable to more complex applications in the area of aerospace embedded systems.
Claims14
An FPGA system comprising:
- a microprocessor;
- a coprocessor with a pseudo-cache,
- a controller;
- a polymorphic systolic array framework comprising a reconfigurable partial region based sockets to accelerate algorithms amenable to being mapped onto linear systolic arrays;
- said microprocessor and said coprocessor and said controller and said polymorphic systolic array framework are communicably coupled;
- wherein EKF and DWT algorithms are mapped onto said architecture;
- and
- on-chip bitstream decompression/relocation methods used to facilitate the dynamic scaling of said polymorphic systolic array framework.
A polymorphic systolic array system comprising:
- reconfigurable partial region based sockets;
- and
- on-chip bitstream decompression/relocation methods are used to facilitate the dynamic scaling of said polymorphic systolic array framework.
A systolic array system comprising:
- reconfigurable partial region based sockets;
- a microprocessor communicably coupled to said reconfigurable partial regions based sockets;
- and
- on-chip bitstream decompression/relocation methods are used to facilitate the dynamic scaling of said polymorphic systolic array framework.
Dependencies are inferred from the claim text.