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US 8,710,862 B2Granted
Programming of DIMM termination resistance values
AssigneeGoogle Inc.
InventorsPhilip Arnold Ferolito, Daniel L. Rosenband, David T. Wang, Michael John Smith
Life of this patent
Estimating the term…
Abstract
Systems, methods, and apparatus, including computer program products, for providing termination resistance in a memory module are provided. An apparatus is provided that includes a plurality of memory circuits; an interface circuit operable to communicate with the plurality of memory circuits and to communicate with a memory controller; and a transmission line electrically coupling the interface circuit to a memory controller, wherein the interface circuit is operable to terminate the transmission line with a single termination resistance that is selected based on a plurality of resistance-setting commands received from the memory controller.
Claims27
A memory subsystem comprising:
- a memory module comprising:
- a first rank of memory circuits comprising a first plurality of memory circuits;
- and
- a second rank of memory circuits comprising a second plurality of memory circuits;
- an interface circuit;
- a first transmission line electrically coupling the interface circuit to a first memory circuit of the first plurality of memory circuits of the first rank;
- and
- a second transmission line electrically coupling the interface circuit to a second memory circuit of the second plurality of memory circuits of the second rank;
- wherein the interface circuit is operable to:
- present the first and the second ranks of memory circuits to a memory controller as a single rank of emulated memory circuits;
- terminate one or more of the first transmission line with the first termination resistance or the second transmission line with the second termination resistance, wherein the first termination resistance and the second termination resistance are each selected based on at least a resistance-setting command for the single rank of emulated memory circuits received from the memory controller, and
- wherein the first termination resistance or the second termination resistance is different from a termination resistance indicated by the resistance-setting command received from the memory controller.
9 more elements
A memory subsystem comprising:
- a memory module comprising:
- a first rank of memory circuits comprising a first plurality of memory circuits;
- and
- a second rank of memory circuits comprising a second plurality of memory circuits;
- an interface circuit;
- a first transmission line electrically coupling the interface circuit to a first memory circuit of the first plurality of memory circuits of the first rank;
- and
- a second transmission line electrically coupling the interface circuit to a second memory circuit of the second plurality of memory circuits of the second rank;
- wherein the interface circuit is operable to:
- present the first and the second ranks of memory circuits to a memory controller as a single rank of emulated memory circuits;
- terminate one or more of the first transmission line with the first termination resistance or the second transmission line with the second termination resistance, wherein the first termination resistance and the second termination resistance are each selected based on at least a resistance-setting command for the single rank of emulated memory circuits received from the memory controller;
- and
- select the first termination resistance and the second termination resistance from one or more look-up tables.
10 more elements
A memory subsystem comprising:
- a memory module comprising:
- a first rank of memory circuits comprising a first plurality of memory circuits;
- and
- a second rank of memory circuits comprising a second plurality of memory circuits;
- an interface circuit;
- a first transmission line electrically coupling the interface circuit to a first memory circuit of the first plurality of memory circuits of the first rank;
- and
- a second transmission line electrically coupling the interface circuit to a second memory circuit of the second plurality of memory circuits of the second rank;
- wherein the interface circuit is operable to:
- present the first and the second ranks of memory circuits to a memory controller as a single rank of emulated memory circuits;
- terminate one or more of the first transmission line with the first termination resistance or the second transmission line with the second termination resistance, wherein the first termination resistance and the second termination resistance are each selected based on at least a resistance-setting command for the single rank of emulated memory circuits received from the memory controller;
- select first resistance values of the first and the second termination resistors for read operations;
- and
- select second, different resistance values of the first and the second termination resistors for write operations.
11 more elements
Dependencies are inferred from the claim text.