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US 8,710,816 B2Granted
Buck converter having reduced ripple under a light load
AssigneeTexas Instruments Incorporated
InventorTakahiro Miyazaki
Life of this patent
Estimating the term…
Abstract
A buck converter and a switching regulator capable of suppressing a ripple voltage under light load conditions. The buck converter has NMOS transistors QN2 and QN3 that are connected in series between input voltage VIN and the ground, inductor L1 that is connected to node SW where transistors QN2 and QN3 are connected, comparator COMP2 that compares respective voltages of node N1 and node N2 so as to decide on time of transistor QN2, and current detection circuit 100 that detects reverse current Ig flowing to the ground from inductor L1 via node SW and transistor QN3. When current detection circuit 100 detects reverse current Ig, voltage of node N1 of comparator COMP2 is reduced by variable circuit 110 in order to reduce the on time of transistor QN2.
Claims20
A buck converter for generating an output voltage lower than the input voltage comprising:
- an inductor connected to a connection node where a first and a second MOS transistor are connected;
- a switching control circuit that controls on time of at least the first MOS transistor;
- and
- a current detection circuit that detects a current flowing from the inductor to a first reference potential via the connection node and the second MOS transistor whereby the switching control circuit controls switching of the first MOS transistor independently of control of the second transistor so as to reduce the on time of the first MOS transistor in response to the detection of a current by the current detection circuit, wherein the on time is reduced to less than being in proportion to the output voltage/the input voltage so that ripple in the output voltage of the buck converter is reduced at light load.
1 more element
A buck converter comprising:
- a first transistor connected between a first power supply terminal and an input node;
- a second transistor connected between a second power supply terminal and the input node;
- an inductor connected between the input node and an output node;
- an output capacitor connected to the output node;
- a first comparison circuit that compares a first voltage corresponding to an output voltage with a first reference voltage and outputs a first signal corresponding to said comparison result;
- a time duration control circuit that outputs a second signal for controlling on time of the first transistor;
- a reverse current detection circuit that detects a reverse current flowing into the input node;
- a first logic circuit that outputs a first control signal for controlling conduction of the first transistor in response to the first signal and the second signal;
- a second logic circuit that outputs a second control signal for controlling conduction of the second transistor in response to the first control signal and the detection signal of the reverse current detection circuit, and
- a time duration adjustment circuit that outputs an adjustment signal for reducing the on time of the first transistor independently of control of the second transistor in response to a detection signal and the first control signal whereby the time duration control circuit outputs the second signal in response to the first control signal and controls output timing of the second signal so as to reduce the on time of the first transistor independently of control of the second transistor upon receiving the adjustment signal, wherein the on time is reduced to less than being in proportion to the output voltage/the input voltage so that ripple in the output voltage of the buck converter is reduced at light load.
7 more elements
A buck converter comprising:
- a first transistor connected between a first power supply terminal and an input node;
- a second transistor connected between a second power supply terminal and the input node;
- an inductor connected between the input node and an output node;
- an output capacitor connected to the output node;
- a first comparison circuit that compares a first voltage corresponding to an output voltage with a first reference voltage and outputs a first signal corresponding to said comparison result;
- a time duration control circuit that outputs a second signal for controlling on time of the first transistor;
- a reverse current detection circuit that detects a reverse current flowing into the input node;
- a first logic circuit that outputs a first control signal for controlling conduction of the first transistor in response to the first signal and the second signal;
- a second logic circuit that outputs a second control signal for controlling conduction of the second transistor in response to the first control signal and the detection signal of the reverse current detection circuit, and
- a time duration adjustment circuit that outputs an adjustment signal for reducing the on time of the first transistor in response to a detection signal and the first control signal whereby the time duration control circuit outputs the second signal in response to the first control signal and controls output timing of the second signal so as to reduce the on time of the first transistor independently of control of the second transistor upon receiving the adjustment signal,
- wherein the time duration control circuit includes a second comparison circuit that compares a voltage signal that changes over time in response to the first control signal with a second reference voltage and outputs the second signal according to said comparison result;
- the reverse current detection circuit includes a third comparison circuit that compares the potential of the input node with a third reference voltage and outputs the detection signal according to said comparison result, and
- the time duration adjustment circuit includes an AND circuit that outputs a signal representing the logical product of the detection signal and the second control signal and a counter circuit that outputs the adjustment signal when the AND signal is input continuously N times.
10 more elements
Dependencies are inferred from the claim text.