Multi-level integrated circuit, device and method for modeling multi-level integrated circuits

A method for manufacturing a multi-level integrated circuit in a superposition of at least a first and second stack of layers of materials, including at least the following steps:

• manufacturing a first row of first electronic devices in the first stack, the first row extending parallel to a first direction and fitting in a first volume with a substantially parallelepiped rectangle shape corresponding to a portion of the first stack and having, in a first plane parallel to a contact surface between the first stack and the second stack, edges perpendicular to the first direction and with dimension H1;
• manufacturing a second row of second electronic devices in the second stack, the second row extending parallel to the first direction and fitting into a second volume with a substantially parallelepiped rectangle shape corresponding to a portion of the second stack, placed on the first volume and having, in said first plane, edges perpendicular to the first direction and with dimension H2 smaller than H1;
• and
• manufacturing a plurality of electrical connection elements electrically connecting inputs and outputs of the first electronic devices of the first row to electrically conductive input/output contacts placed above the second stack, passing through the second stack of layers, each connection element fitting into a third volume corresponding to a portion of the second stack and being placed on the first volume next to the second volume.