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US 8,710,665 B2Granted
Electronic component, a semiconductor wafer and a method for producing an electronic component
AssigneeInfineon Technologies AG
InventorFriedrich Kroener
Life of this patent
Estimating the term…
Abstract
An electronic component includes a semiconductor substrate defined by a generally planar first face, a generally planar second face and side faces extending between the generally planar second face and the generally planar first face. The semiconductor substrate has a curved contour between the generally planar second face and the side faces.
Claims17
An electronic component including a semiconductor substrate, the semiconductor substrate comprising:
- a generally planar first face;
- a generally planar second face situated parallel to the generally planar first face;
- side faces extending from the generally planar first face;
- a curved contour extending from the generally planar second face to the side faces;
- and
- a metallic layer arranged on, and entirely covering, the second face, the curved contour and the side faces, the metallic layer in direct contact with the second face, the curved contour and the side faces,
- wherein the semiconductor substrate includes a peripheral layer of a first conductivity type extending along the second face and the side faces and bounding a central region of the first conductivity type, the peripheral layer being more highly doped than the central region, and
- wherein the semiconductor component is one of a MOS-controlled transistor and a diode.
5 more elements
A semiconductor wafer comprising:
- a plurality of semiconductor components, each including a semiconductor substrate comprising:
- a generally planar first face;
- a generally planar second face situated parallel to the generally planar first face;
- side faces extending from the generally planar first face;
- a curved contour extending from the generally planar second face and the side faces;
- and
- a metallic layer arranged on, and entirely covering, the second face, the curved contour and the side faces, the metallic layer in direct contact with the second face, the curved contour and the side faces,
- wherein the semiconductor substrate includes a peripheral layer of a first conductivity type extending along the second face and the side faces and bounding a central region of the first conductivity type, the peripheral layer being more highly doped than the central region,
- wherein each semiconductor component is one of a MOS-controlled transistor and a diode, and
- wherein the plurality of semiconductor components are joined to their immediate neighbor by a metallization layer arranged on the generally planar first face.
7 more elements
An electronic component comprising:
- a vertical MOS-controlled transistor;
- a semiconductor substrate having generally planar first face, a generally planar second face situated parallel to the generally planar first face and side faces extending from the generally planar first face;
- a curved contour extending from the generally planar second face to the side faces;
- the semiconductor substrate including an outermost edge region of a first conductivity type extending along the second face and along the side faces and bounding a central region of the first conductivity type, the outermost edge region being more highly doped than the central region and providing a load electrode of the vertical MOS-controlled transistor;
- and
- a metallic layer encapsulating the second face and the side faces, the metallic layer in direct contact with the outermost edge region of the first conductivity type extending along the second face and along the side faces.
3 more elements
A vertical MOSFET device, comprising:
- a substrate including a planar first face, a second face situated parallel to the first face, and side faces extending from the first face to the second face with a curved contour extending from the second face to the side faces;
- a source contact situated on the first face and having a first area;
- a gate contact situated on the first face spaced apart and electrically isolated from the source contact, the gate contact having a second area smaller than the first area;
- a peripheral layer encapsulating the second face and the side faces, the peripheral layer extending to the first face and outwardly from the side faces to form a peripheral region;
- a drain contact having a first portion situated on the first face and a second portion extending outwardly from the side faces, such that the peripheral region is positioned over the second portion of the drain contact.
2 more elements
A semiconductor wafer comprising:
- a plurality of semiconductor components, each including a semiconductor substrate comprising:
- a generally planar first face;
- a generally planar second face situated parallel to the generally planar first face;
- side faces extending from the generally planar first face;
- and
- a curved contour extending from the generally planar second face and the side faces;
- a source contact situated on the first face and having a first area;
- a gate contact situated on the first face spaced apart and electrically isolated from the source contact, the gate contact having a second area smaller than the first area;
- a peripheral layer encapsulating the second face and the side faces, the peripheral layer extending to the first face and outwardly from the side faces to form a peripheral region;
- a drain contact having a first portion situated on the first face and a second portion extending outwardly from the side faces, such that the peripheral region is positioned over the second portion of the drain contact;
- wherein the plurality of semiconductor components are joined to their immediate neighbor by a metallization layer arranged on the generally planar first face.
8 more elements
Dependencies are inferred from the claim text.