Wafer-level chip scale package
AssigneeVolterra Semiconductor Corporation
InventorsEfren M. Lacap, Subhash Rewachand Nariani, Charles Nickel
Life of this patent
Estimating the term…
Abstract
A chip scale package implements solder bars to form a connection between a chip and a trace, formed in a substrate, such as another chip or PCB. Solder bars are formed by depositing one or more solder layers into the socket, or optionally, depositing a base metal layer into the socket and applying the solder layer to the base metal layer. The geometry of a solder bars may be rectangular, square, or other regular or irregular geometry. Solder bars provide a greater utilization of the connectivity footprint and increase the electrical and thermal flow capacity. Solder bars also provide a robust connection.
Claims10
A chip scale package made-ready for installation of a microchip on a printed circuit board, an interposer, or a chip-on-chip stack, comprising:
- a microchip including a switching element;
- a first solder bar electrically coupled to a first terminal of the switching element;
- a second solder bar electrically coupled to a second terminal of the switching element;
- and
- a plurality of additional solder bars, each of the plurality of additional solder bars configured to provide an interface with the microchip for a signal selected from the group consisting of a data signal and an input/output signal;
- wherein:
- the first solder bar comprises a plurality of first solder bars,
- the second solder bar comprises a plurality of second solder bars, and
- the plurality of first solder bars is disposed in an alternating sequence with the plurality of second solder bars.
A chip scale package made-ready for installation of a microchip on a printed circuit board, an interposer, or a chip-on-chip stack, comprising:
- a microchip including a switching element;
- a first solder bar electrically coupled to a first terminal of the switching element;
- a second solder bar electrically coupled to a second terminal of the switching element;
- and
- a plurality of additional solder bars, each of the plurality of additional solder bars configured to provide an interface with the microchip for a signal selected from the group consisting of a data signal and an input/output signal;
- wherein:
- the first solder bar comprises a plurality of first solder bars,
- the second solder bar comprises a plurality of second solder bars,
- the chip scale package comprises a plurality of third solder bars,
- each of the plurality of first solder bars is electrically coupled to a first node in the microchip, each of the plurality of second solder bars is electrically coupled to a second node in the microchip, and each of the plurality of third solder bars is electrically coupled to a third node in the microchip, each of the first, second, and third nodes being different nodes,
- a first column of solder bars includes an alternating sequence of the plurality of first solder bars and the plurality of second solder bars, and
- a second column of solder bars includes an alternating sequence of the plurality of second solder bars and the plurality of third solder bars.
A chip scale package made-ready for installation of a microchip on a printed circuit board, an interposer, or a chip-on-chip stack, comprising:
- a microchip;
- first and second solder bars configured to provide power circuit connections to the microchip;
- and
- a plurality of additional solder bars, each of the plurality of additional solder bars configured to provide an interface with the microchip for a signal selected from the group consisting of a data signal and an input/output signal;
- wherein:
- the first solder bar comprises a plurality of first solder bars,
- the second solder bar comprises a plurality of second solder bars, and
- the plurality of first solder bars is disposed in an alternating sequence with the plurality of second solder bars.
A chip scale package made-ready for installation of a microchip on a printed circuit board, an interposer, or a chip-on-chip stack, comprising:
- a microchip;
- first and second solder bars configured to provide power circuit connections to the microchip;
- and
- a plurality of additional solder bars, each of the plurality of additional solder bars configured to provide an interface with the microchip for a signal selected from the group consisting of a data signal and an input/output signal;
- wherein:
- the first solder bar comprises a plurality of first solder bars,
- the second solder bar comprises a plurality of second solder bars,
- the chip scale package comprises a plurality of third solder bars,
- each of the plurality of first solder bars is electrically coupled to a first node in the microchip, each of the plurality of second solder bars is electrically coupled to a second node in the microchip, and each of the plurality of third solder bars is electrically coupled to a third node in the microchip, each of the first, second, and third nodes being different nodes,
- a first column of solder bars includes an alternating sequence of the plurality of first solder bars and the plurality of second solder bars, and
- a second column of solder bars includes an alternating sequence of the plurality of second solder bars and the plurality of third solder bars.
A chip scale package made-ready for installation of a microchip on a printed circuit board, an interposer, or a chip-on-chip stack, comprising:
- a microchip including a switching element;
- a plurality of first solder bars electrically coupled to a first terminal of the switching element;
- and
- a plurality of second solder bars electrically coupled to a second terminal of the switching element;
- wherein:
- each first and second solder bar forms a respective surface for soldering to a bonding surface, and
- the plurality of first solder bars is disposed in an alternating sequence with the plurality of second solder bars.
A chip scale package made-ready for installation of a microchip on a printed circuit board, an interposer, or a chip-on-chip stack, comprising:
- a microchip including a switching element;
- a plurality of first solder bars electrically coupled to a first terminal of the switching element;
- a plurality of second solder bars electrically coupled to a second terminal of the switching element;
- and
- a plurality of third solder bars;
- wherein:
- each solder bar forms a respective surface for soldering to a bonding surface,
- each of the plurality of first solder bars is electrically coupled to a first node in the microchip, each of the plurality of second solder bars is electrically coupled to a second node in the microchip, and each of the plurality of third solder bars is electrically coupled to a third node in the microchip, each of the first, second, and third nodes being different nodes,
- a first column of solder bars includes an alternating sequence of the plurality of first solder bars and the plurality of second solder bars, and
- a second column of solder bars includes an alternating sequence of the plurality of second solder bars and the plurality of third solder bars.
Dependencies are inferred from the claim text.