Under bump passive components in wafer level packaging

A packaged semiconductor device comprising:

• a semiconductor die;
• and
• a plurality of post-processing layers deposited onto an active face of the semiconductor die, the plurality of post-processing layers comprising:
• a first dielectric layer, a first metal layer, a second dielectric layer and a second metal layer deposited sequentially, with the first dielectric layer formed on the active face of the semiconductor die and the first and second metal layers patterned to form tracks and lands;
• wherein the second metal layer comprises a plurality of lands for solder bumps and the first dielectric layer comprises an array of openings in the layer underneath a land for a solder bump, and the packaged semiconductor device further comprising:
• a capacitor underneath at least one land for a solder bump and over an array of openings in the first dielectric layer, the capacitor comprising a layer of the second dielectric between the land in the second metal layer and an area of the first metal layer and wherein the layers in the capacitor are non-planar and follow a topology over the array of openings in the first dielectric layer such that a portion of the first metal layer is in contact with the active face of the semiconductor die within each opening and another portion of the first metal layer is in contact with the first dielectric layer between openings.