Semiconductor assembly and semiconductor package including a solder channel

A semiconductor assembly comprising:

• a semiconductor chip comprising a connection pad on a surface thereof;
• a first pillar, on the semiconductor chip, comprising a solder channel on a side thereof;
• a first solder ball on the first pillar, wherein the first pillar is between the first solder ball and the semiconductor chip, and a portion of the first solder ball extends into the solder channel and covers at least a portion of the side of the first pillar;
• a passivation layer, on the semiconductor chip, extending between the first pillar and the semiconductor chip and comprising an opening exposing the connection pad;
• a second pillar, on the semiconductor chip, contacting the connection pad and comprising a non-solder-channel pillar;
• and
• a second solder ball on the second pillar, wherein the second pillar is between the second solder ball and the semiconductor chip,
• wherein the first pillar is immediately adjacent to the second pillar and the solder channel faces away from the second pillar.

A semiconductor package comprising:

• a plurality of connection pads on a surface of a semiconductor chip;
• a plurality of first bumps on and configured to be electrically connected to the plurality of connection pads, wherein each of the plurality of first bumps comprises a first solder ball and a first pillar between the first solder ball and one of the plurality of connection pads;
• a plurality of second bumps on the semiconductor chip and configured to be electrically isolated from the plurality of connection pads, wherein each of the plurality of second bumps comprises a second solder ball and a second pillar between the second solder ball and the semiconductor chip, and the second pillar comprises a solder channel configured to allow a portion of the second solder ball to extend into the solder channel;
• and
• a passivation layer on the surface of the semiconductor chip, wherein the passivation layer comprises a plurality of openings exposing respective ones of the plurality of connection pads and extends between the plurality of second bumps and the semiconductor chip, and wherein the plurality of first bumps contact respective ones of the plurality of connection pads.