Redistribution layer (RDL) with variable offset bumps

An integrated circuit (IC) chip comprising:

• a semiconductor substrate having a plurality of metal vertical interconnect accesses (vias) in a back end of line (BEOL) layer;
• a redistribution layer (RDL) on the BEOL layer;
• a plurality of bond pads on the RDL, each bond pad connected to a corresponding metal via through the RDL;
• and
• a solder bump connected to each bond pad, wherein each solder bump is laterally offset from the corresponding metal via connected to the bond pad towards a center of the IC chip by an offset distance, wherein the offset distance for each solder bump is proportionate to a distance between the center of the IC chip and the center of the corresponding metal via for that solder bump.

A method for non-uniformly offsetting solder bumps on an integrated circuit (IC) chip, the method comprising:

• providing a semiconductor substrate having a plurality of metal vertical interconnect accesses (vias) in a back end of line (BEOL) layer;
• forming a redistribution layer (RDL) on the BEOL layer;
• forming a plurality of bond pads on the RDL, each bond pad connected to a corresponding metal via through the RDL;
• and
• positioning a solder bump on each solder bump pad structure such that each solder bump is laterally offset from the corresponding metal via connected to the bond pad towards a center of the IC chip by an offset distance, wherein the offset distance is non-uniform across the IC chip, and wherein the offset distance for solder bumps proximate to an edge of the IC chip is larger than the offset distance of solder bumps in an interior of the IC chip.