Semiconductor device and method for manufacturing the same

A method for manufacturing a semiconductor device, comprising:

• bonding a semiconductor chip to a substrate via a plurality of bumps, with a device formation face of said semiconductor chip facing one face of said substrate;
• and
• filling a space between said device formation face of said semiconductor chip and said one face of said substrate with a resin,
• said filling said space including:
• forming a first resin in a formation region of the plurality of bumps placed on an outermost circumference of said plurality of bumps and inside said formation region, said first resin having a lower thermal expansion coefficient than a thermal expansion coefficient of said substrate;
• and
• forming a second resin outside said first resin and contacting said first resin, said second resin having a higher thermal expansion coefficient than said thermal expansion coefficient of said first resin, the thermal expansion coefficient of the second resin being α1>40 ppm/° C., α2>150 ppm/° C., with α1 being the linear expansion coefficient when a temperature is lower than Tg, and α2 being the linear expansion coefficient when the temperature is equal to or higher than Tg, achieved by a wt % content ratio of inorganic filler in the second resin being lower than that of the first resin or a maximum particle size of the inorganic filler in the second resin being smaller than that of the first resin, wherein,
• an outside perimeter of said first resin is located more inward than an outer perimeter of said semiconductor chip, and
• an inside perimeter of said second resin is located more inward than the outer perimeter of said semiconductor chip, the outside perimeter of said first resin contacting the inside perimeter of said second resin with an interface between said first and second resins being located below said semiconductor chip more inward than the outer perimeter of said semiconductor chip.

A semiconductor device comprising:

• a substrate;
• a semiconductor chip that is bonded to one face of said substrate via a plurality of bumps, and has a device formation face facing said one face;
• and
• a resin that fills a space between said device formation face of said semiconductor chip and said one face of said substrate,
• said resin including:
• a first resin that is formed in a formation region of the plurality of bumps placed on an outermost circumference of said plurality of bumps, and is formed inside said formation region;
• and
• a second resin that is formed outside said first resin, the second resin contacting said first resin,
• a thermal expansion coefficient of said substrate being higher than a thermal expansion coefficient of said first resin, and
• a thermal expansion coefficient of said second resin being higher than said thermal expansion coefficient of said first resin, the thermal expansion coefficient of the second resin being α1>40 ppm/° C., α2>150 ppm/° C., with α1 being the linear expansion coefficient when a temperature is lower than Tg, and α2 being the linear expansion coefficient when the temperature is equal to or higher than Tg, achieved by a wt % content ratio of inorganic filler in the second resin being lower than that of the first resin or a maximum particle size of the inorganic filler in the second resin being smaller than that of the first resin.