Wafer level packaging structure with large contact area and preparation method thereof
AssigneeAlpha and Omega Semiconductor Incorporated
InventorYan Xun Xue
Life of this patent
Estimating the term…
Abstract
A method to provide a wafer level package with increasing contact pad area comprising the steps of forming a first packaging layer on wafer top surface, grinding the wafer back surface and etch through holes, depositing a metal to fill the through holes and covering wafer backside, cutting through the wafer from wafer backside forming a plurality of grooves separating each chip then depositing a second packaging layer filling the grooves and covering the wafer back metal, reducing the first packaging layer thickness to expose the second packaging layer filling the grooves and forming a plurality of contact pads overlaying the first packaging layer thereafter cutting through the second packaging layer in the grooves to form individual package.
Claims9
A method for preparing a wafer level packaging structure with large contact area, wherein a plurality of first metal bonding pads are formed at a front surface of semiconductor chips formed in a semiconductor wafer, comprising the following steps:
- forming at least a second metal bonding pad at the front surface of each chip;
- forming a first packaging layer covering the first metal bonding pads and the second metal bonding pads and the front surface of the wafer;
- etching from a back surface of the wafer to form a bottom through hole to expose the second metal bonding pad in the chip and filling a conductive material in the bottom through hole to form a bottom metal interconnecting structure connected to the second metal bonding pad;
- forming a metal layer covering the back surface of the wafer connected to the bottom metal interconnecting structure;
- cutting through the wafer and the metal layer from the back surface of the wafer to form a plurality of cutting grooves, wherein the cutting grooves extend into the first packaging layer and separate individual chips from each other, and wherein the metal layer is cut into a plurality of bottom metal layers, each of which covers the back surface of each chip;
- depositing a packaging material to form a second packaging layer covering the bottom metal layers and to fill into the cutting groove;
- thinning the first packaging layer until the packaging material filled in the cutting groove being exposed, whereby forming a plurality of top packaging layers, each of which covers the front surface of each chip;
- etching the top packaging layer to expose the first metal bonding pads and the second metal bonding pad thus forming a plurality of top through holes above the first metal bonding pads and the second metal bonding pad and filing a conductive material into the top through holes to form a plurality of top metal interconnecting structures connected to the first metal bonding pads and the second metal bonding pad respectively;
- forming a plurality of contact bonding pads atop the first packaging layer, wherein one contact bonding pad is electrically connected to one first metal bonding pad or one second metal bonding pad through at least one top metal interconnecting structure;
- and
- cutting through the second packaging layer and the packaging material filled in the cutting groove along the cutting groove to separate individual wafer level packaging structures from each other, wherein the second packaging layer is cut into a plurality of bottom packaging layers, each of which covers the bottom metal layer of each chip.
Dependencies are inferred from the claim text.