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US 8,710,645 B2Granted
Area reduction for surface mount package chips
OwnerJeng-Jye Shauinventor
Life of this patent
Estimating the term…
Abstract
Using side-wall conductor leads insulated by side-wall insulators to form package level conductor leads for active circuits manufactured on silicon substrate, the preferred embodiments of the present invention significantly reduces the areas of surface mount package chips. Besides area reduction, these methods also provide significant cost saving and reduction in parasitic impedance.
Claims17
A surface mount package chip, comprising:
- a silicon substrate;
- active electrical device(s) formed on the silicon substrate;
- side-wall conductor leads extend from a soldering surface of the active electrical device(s) through a top surface of the silicon substrate to the side-wall(s) wherein the side-wall conductor leads are further deposited on and extends over at least 60% of a sidewall depth of the side-wall(s) of the surface mount package chip providing external connections to the active device(s) on the silicon substrate;
- side-wall insulator(s) deposited on the side-wall(s) of the surface mount package chip providing electrical insulating between the silicon substrate and the side-wall conductor leads;
- and wherein the side-wall insulator(s) comprise dried-ink insulator(s).
2 more elements
A surface mount package chip comprising:
- a silicon substrate;
- active electrical device(s) formed on the silicon substrate;
- side-wall conductor leads extend from a soldering surface of the active electrical device(s) through a top surface of the silicon substrate to the side-wall(s) wherein the side-wall conductor leads are further deposited on and extends over at least 60% of a sidewall depth of the side-wall(s) of the surface mount package chip providing external connections to the active device(s) on the silicon substrate;
- side-wall insulator(s) deposited on the side-wall(s) of the surface mount package chip providing electrical insulating between the silicon substrate and the side-wall conductor leads;
- and wherein the side-wall insulator(s) comprise photo-resist material(s).
2 more elements
A method for manufacturing a surface mount package chip, comprising the steps of:
- fabricating active electrical device(s) on a silicon substrate;
- placing the silicon substrate in the surface mount package chip;
- forming side-wall insulator(s) by depositing dried-ink insulator(s) on the side-wall(s) of the surface mount package chip;
- forming side-wall conductor leads to extend from a soldering surface of the active electrical device(s) through a top surface of the surface mount chip to over at least 60% of a sidewall depth of the side-wall(s) of the surface mount package chip for providing external connections to the active electrical device(s) on the silicon substrate.
1 more element
A method for manufacturing a surface mount package chip, comprising the steps of:
- fabricating active electrical device(s) on a silicon substrate;
- placing the silicon substrate in the surface mount package chip;
- forming side-wall insulator(s) by depositing photo-resist material(s) on the side-wall(s) of the surface mount package chip;
- forming side-wall conductor leads to extend from a soldering surface of the active electrical device(s) through a top surface of the surface mount chip to over at least 60% of a sidewall depth of the side-wall(s) of the surface mount package chip.
1 more element
Dependencies are inferred from the claim text.