Back to results
US 8,710,636 B1Granted
Lead frame array package with flip chip die attach
AssigneeFreescale Semiconductor, Inc.
InventorCaleb C. Han
Life of this patent
Estimating the term…
Abstract
A small form factor near chip scale package is provided that includes input/output contacts not only along the periphery of the package, but also along the package bottom area. Embodiments provide these additional contacts through use of an array lead frame coupled to under die signal contacts through the use of flip chip bonding techniques. The array lead frame contacts are electrically isolated through the use of a partial sawing process performed during package singulation.
Claims9
An array lead frame for a semiconductor device package, the array lead frame comprising:
- a first row of a first plurality of edge leads;
- a second row of a second plurality of edge leads;
- a third row of a third plurality of center leads;
- a first set of tie bars coupling a center lead of the third plurality of center leads to one or more edge leads of the first plurality of edge leads;
- and
- a second set of tie bars coupling the center lead of the third plurality of center leads to one or more edge leads of the second plurality of edge leads,
- wherein
- each lead is configured for electrical coupling to a corresponding die bonding pad using a flip chip die attach.
5 more elements
A semiconductor device package comprising:
- an array lead frame comprising
- a first row of a first plurality of edge leads,
- a second row of a second plurality of edge leads,
- a third row of a third plurality of center leads,
- a first set of tie bars coupling a center lead of the third plurality of center leads to one or more edge leads of the first plurality of edge leads,
- a second set of tie bars coupling the center lead of the third plurality of center leads to one or more edge leads of the second plurality of edge leads;
- a semiconductor device die comprising a first major surface and a plurality of bond pads on the first major surface, wherein
- each bond pad is located in a geometric location corresponding to an edge lead or center lead of the array lead frame, and
- each bond pad is electrically coupled to the corresponding edge lead or center lead of the array lead frame;
- and
- a mold compound formed over and around the semiconductor device die and encapsulating a portion of each lead of the array lead frame.
8 more elements
Dependencies are inferred from the claim text.