US 8,710,627 B2Granted

Uni-directional transient voltage suppressor (TVS)

AssigneeAlpha and Omega Semiconductor Incorporated

InventorsLingpeng Guan, Madhur Bobde, Anup Bhalla

Life of this patent

Estimating the term…

Loading patent…

Abstract

An epitaxial layer is supported on top of a substrate. First and second body regions are formed within the epitaxial layer separated by a predetermined lateral distance. Trigger and source regions are formed within the epitaxial layer. A first source region is transversely adjacent the first body region between first and second trigger regions laterally adjacent the first source region and transversely adjacent the first body region. A second source region is located transversely adjacent the second body region between third and fourth trigger regions laterally adjacent the second source region and transversely adjacent the second body region. A third source region is laterally adjacent the fourth trigger region. The fourth trigger region is between the second and third source regions. An implant region within the fourth trigger region is laterally adjacent the third source region.

Claims28

Dependent claims

A unidirectional transient voltage suppressor (TVS) device comprising:

a) a semiconductor substrate of a first conductivity type;
b) an epitaxial layer of the first conductivity type formed on the substrate;
c) a first and second body regions of a second conductivity type that is opposite to the first conductivity type formed within the epitaxial layer, the first and second body regions being separated laterally by a predetermined distance;
d) a set of trigger regions of the second conductivity type formed within a surface of the epitaxial layer;
e) a set of source regions of the first conductivity type formed within a surface of the epitaxial layer, the trigger regions and source regions including a first source region located transversely adjacent the first body region between first and second trigger regions that are laterally adjacent the first source region and transversely adjacent the first body region, a second source region located transversely adjacent the second body region between third and fourth trigger regions that are laterally adjacent the second source region and transversely adjacent the second body region, and a third source region located laterally adjacent the fourth trigger region, wherein the fourth trigger region is between the second and third source regions;
and
f) an implant region of the second conductivity type located within the fourth trigger region, the implant region being laterally adjacent the third source region and having a doping concentration higher than that of the trigger region,
wherein the implant region of the second conductivity type and the third source region cause a short circuit from the second body region to portions of the semiconductor substrate and the epitaxial layer of the first conductivity type.

5 more elements

A method for manufacturing a unidirectional transient voltage suppressor (TVS) device, comprising:

a) forming an epitaxial layer of a first conductivity type on top of a substrate of the first conductivity type;
b) forming a first body region and a second body region of a second conductivity type opposite to the first conductivity type within the epitaxial layer;
c) forming a set of trigger regions of the second conductivity within a surface of the epitaxial layer;
e) forming a set of source regions of the first conductivity type within a surface of the epitaxial layer, the trigger regions and source regions including a first source region located transversely adjacent the first body region between first and second trigger regions that are laterally adjacent the first source region and transversely adjacent the first body region, a second source region located transversely adjacent the second body region between third and fourth trigger regions that are laterally adjacent the second source region and transversely adjacent the second body region, and a third source region located laterally adjacent the fourth trigger region, wherein the fourth trigger region is between the second and third source regions;
and
f) forming an implant region of the second conductivity type within the fourth trigger region, the implant region being laterally adjacent the third source region and having a doping higher concentration higher than that of the trigger region,
wherein the implant region of the second conductivity type and the third source region cause a short circuit from the second body region to portions of the semiconductor substrate and the epitaxial layer of the first conductivity type.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/171,037Filed 28 Jun 2011
Published: US 2013/0001695 A13 Jan 2013
Granted: 29 Apr 2014
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

H10D 89/713
Using bipolar transistors as protective elements: including a PNP transistor and a NPN transistor, wherein each of said transistors has its base…
H10D 84/0112
Manufacture or treatment: integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs
H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe
H10D 84/221
Of combinations of diodes or capacitors or resistors: of only diodes