SONOS stack with split nitride memory layer
AssigneeCypress Semiconductor Corporation
InventorsFredrick Jenne, Krishnaswamy Ramkumar
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Abstract
Embodiments of a non-planar memory device including a split charge-trapping region and methods of forming the same are described. Generally, the device comprises: a channel formed from a thin film of semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device; a tunnel oxide overlying the channel; a split charge-trapping region overlying the tunnel oxide, the split charge-trapping region including a bottom charge-trapping layer comprising a nitride closer to the tunnel oxide, and a top charge-trapping layer, wherein the bottom charge-trapping layer is separated from the top charge-trapping layer by a thin anti-tunneling layer comprising an oxide. Other embodiments are also disclosed.
Claims20
A memory device comprising:
- a channel formed from a thin film of semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device;
- a tunnel oxide overlying the channel;
- a split charge-trapping region overlying the tunnel oxide, the split charge-trapping region including a bottom charge-trapping layer comprising a nitride closer to the tunnel oxide, and a top charge-trapping layer, wherein the bottom charge-trapping layer is separated from the top charge-trapping layer by a thin anti-tunneling layer comprising an oxide,
- wherein the top charge-trapping layer comprises a silicon-rich, oxygen-lean nitride, the bottom charge-trapping layer comprises an oxygen-rich nitride, and further comprising a blocking dielectric layer overlying the split charge-trapping region.
A memory device comprising:
- a channel formed from a thin film of semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device;
- a tunnel oxide overlying the channel;
- a split charge-trapping region overlying the tunnel oxide, the split charge-trapping region including a bottom charge-trapping layer comprising a nitride closer to the tunnel oxide, and a top charge-trapping layer, wherein the bottom charge-trapping layer is separated from the top charge-trapping layer by a thin anti-tunneling layer comprising an oxide,
- wherein the channel projects above the surface on the substrate, and further comprising a fin intersecting and overlying at least a portion of the channel, the fin comprising the tunnel oxide and the split charge-trapping region overlying the tunnel oxide, and
- wherein the top charge-trapping layer comprises a silicon-rich, oxygen-lean nitride, the bottom charge-trapping layer comprises an oxygen-rich nitride layer, and further comprising a blocking oxide layer overlying the split charge-trapping region.
A memory device comprising:
- a vertical channel formed from a thin projection of semiconducting material extending from a first diffusion region formed on a surface on a substrate to a second diffusion region formed over the surface of the substrate, the vertical channel electrically connecting the first diffusion region to the second diffusion region;
- a tunnel oxide abutting the vertical channel;
- a split charge-trapping region abutting the tunnel oxide, the split charge-trapping region including a first charge-trapping layer comprising an oxygen-rich nitride closer to the tunnel oxide, and a second charge-trapping layer comprising a silicon-rich, oxygen-lean nitride overlying the first charge-trapping layer,
- wherein the second charge-trapping layer comprises a majority of a charge traps distributed in split charge-trapping region.
A process of manufacturing a semiconductor device, the process comprising:
- forming a channel from a thin film of semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device;
- forming a tunnel oxide overlying the channel;
- forming a split charge-trapping region over the tunnel oxide including a bottom charge-trapping layer comprising an oxygen-rich nitride overlying the tunnel oxide, a thin anti-tunneling layer comprising an oxide overlying the tunnel oxide bottom charge-trapping layer, and a top charge-trapping layer comprising a silicon-rich, oxygen-lean nitride overlying the thin anti-tunneling layer,
- wherein the top charge-trapping layer comprises a majority of a charge traps distributed in split charge-trapping region.
Dependencies are inferred from the claim text.