US 8,710,552 B2Granted

Semiconductor device

AssigneeRenesas Electronics Corporation

InventorsNobuhiro Tsuda, Hidekatsu Nishimaki, Hiroshi Omura, Yuko Yoshifuku

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Abstract

A pMIS region is provided between a boundary extending in a first direction and passing through each of a plurality of standard cells and a first peripheral edge. An nMIS region is provided between the boundary and a second peripheral edge. A power supply wiring and a grounding wiring extend along the first and second peripheral edges, respectively. A plurality of pMIS wirings and a plurality of nMIS wirings are arranged on a plurality of first virtual lines and a plurality of second virtual lines, respectively, extending in the first direction and arranged with a single pitch in a second direction. The first virtual line that is the closest to the boundary and the second virtual line that is the closest to the boundary have therebetween a spacing larger than the single pitch.

Claims12

Dependent claims

A semiconductor device including a region functionally defined by a plurality of cells arranged in a first direction to fill a region between first and second cell boundaries mutually spaced and extending in said first direction, the semiconductor device comprising:

a semiconductor substrate;
and
a plurality of gate electrodes extending on said semiconductor substrate in a second direction orthogonal to said first direction, and arranged in each of said plurality of cells with a first pitch in said first direction, said plurality of cells each having a width of an internal multiple of said first pitch in said first direction, wherein:
said cells each include a first region and a second region, said first region being sandwiched by said first cell boundary and said second region, said second region being sandwiched by said first region and said second cell boundary;
and
said semiconductor substrate includes in said first region a first well of a first conduction type, and includes in said second region a second well of a second conduction type different from said first conduction type, the semiconductor device further comprising:
a first diffusion region provided on a portion of said first well and being of said second conduction type;
and
a second diffusion region provided on a portion of said second well and being of said first conduction type.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/538,602Filed 29 Jun 2012 · division
Priority: JP 2008-21033219 Aug 2008
Published: US 2012/0261723 A118 Oct 2012
Granted: 29 Apr 2014
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

H10D 84/859
Complementary IGFETs, e.g. CMOS: comprising both N-type and P-type wells, e.g. twin-tub
H10D 84/85
Of only insulated-gate FETs [IGFET]: complementary IGFETs, e.g. CMOS
H10D 84/903
Masterslice integrated circuits: comprising field effect technology
H10D 84/998
Masterslice integrated circuits: input and output buffer/driver structures

Family

Application12/536,319Parent of this division · filed 5 Aug 2009
US 2012/0261723 A1Pre-grant publication · published 18 Oct 2012
US 8,237,203 B2Parent of this division
US 2010/0044755 A1Published application
US 8,710,552 B2This patent

From the US filing history. Foreign family members aren’t listed.