US 8,709,937 B2 · Method of forming micropattern, method of forming damascene metallization, and semiconductor device and semiconductor memory device fabricated using the same

Abstract

According to example embodiments, a method of forming micropatterns includes forming dummy patterns having first widths on a dummy region of a substrate, and forming cell patterns having second widths on an active line region of the substrate. The active line region may be adjacent to the dummy region and the second widths may be less than the first widths. The method may further include forming damascene metallization by forming a seed layer on the active line region and the dummy region, forming a conductive material layer on a whole surface of the substrate, and planarizing the conductive material layer to form metal lines.

Claims22

Dependent claims

A method of forming micropatterns, comprising:

forming a first mask on a substrate,
the substrate including a dummy region adjacent to an active line region,
the first mask covering at least a part of the dummy region and exposing a portion of the substrate;
forming mold mask patterns on the first mask and the exposed portion of the substrate;
forming spacers on sidewalls of the mold mask patterns;
forming second masks by removing a part of the first mask exposed through the mold mask patterns and the spacers;
removing the mold mask patterns;
and
forming micropatterns by etching the substrate using the spacers and the second masks as etch masks.

6 more elements

A method of forming micropatterns, comprising:

forming mold mask patterns on a substrate,
the mold mask patterns including at least two first mold structures on an active line region of the substrate and at least two second mold structures on a dummy region of the substrate,
the at least two first and second mold structures each having sidewalls;
forming a spacer pattern including,
first spacers on the sidewalls of the at least two first mold structures, and
second spacers on the sidewalls of the at least two second mold structures, forming micropatterns by,
removing the at least two first mold structures;
removing a portion of the active line region of the substrate not covered by the first spacers after the removing the at least two first mold structures, and
removing a portion of the dummy region of the substrate not covered by the at least two second mold structures and the second spacers.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application

13/533,653Filed 26 Jun 2012

Priority

KR 10-2011-00668656 Jul 2011

Published

US 2013/0012023 A110 Jan 2013

Granted

29 Apr 2014

Term ends

Not estimatedThe source records don’t support an estimate.

Classification13 codes

H10W 72/00
Interconnections or connectors in packages
H10B 43/10
EEPROM devices comprising charge-trapping gate insulators: characterised by the top-view layout
H10B 43/35
Characterised by the memory core region: with cell select transistors, e.g. NAND
H10D 62/10
Semiconductor bodies, or regions thereof, of devices having potential barriers: shapes, relative sizes or dispositions of the regions of the…

Method of forming micropattern, method of forming damascene metallization, and semiconductor device and semiconductor memory device fabricated using the same

Life of this patent

Method of forming micropattern, method of forming damascene metallization, and semiconductor device and semiconductor memory device fabricated using the same

Life of this patent

Abstract

Claims22