Integrated circuit packaging system with interconnects and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system comprising:

• providing a carrier, having a carrier first side and a carrier second side, with a contact pad along the carrier first side, the contact pad having a contact width;
• forming a first resist layer, having a first resist opening, over the carrier first side and the contact pad, the first resist opening partially exposing the contact pad, the first resist opening less than the contact width;
• forming a second resist layer, having a second resist opening over the first resist opening, the second resist opening exposing the first resist layer and forming a horizontal step between the second resist layer and the first resist layer, the second resist opening greater than the first resist opening and substantially equivalent to the contact width;
• mounting an integrated circuit over the carrier first side;
• and
• forming an internal interconnect between the integrated circuit and the carrier, the internal interconnect filling the first resist opening and the second resist opening with no space between the second resist layer in the second resist opening.

An integrated circuit packaging system comprising:

• a carrier having a contact pad with a contact width;
• a first resist layer, having a first resist opening, over the carrier and the contact pad, the first resist opening partially exposing the contact pad, the first resist opening less than the contact width;
• a second resist layer, having a second resist opening, over the first resist layer, the second resist opening exposing the first resist layer and forming a horizontal step between the second resist layer and the first resist layer, the second resist opening greater than the first resist opening and substantially equivalent to the contact width;
• an integrated circuit mounted over the carrier;
• and
• an internal interconnect between the integrated circuit and the carrier, the internal interconnect filling the first resist opening and the second resist opening with no space between the second resist layer in the second resist opening.