Silicon-on-insulator (SOI) structure configured for reduced harmonics and method of forming the structure

A method of forming a semiconductor structure comprises:

• forming a semiconductor substrate having a first surface and a second surface opposite said first surface, said forming of said semiconductor substrate comprising, during said forming of said semiconductor substrate, doping said semiconductor substrate with a first concentration of a dopant having a given conductivity type;
• forming an insulator layer on and immediately adjacent to a second surface of said substrate above said first surface;
• implanting one of said dopant and a different dopant having said given conductivity type into said semiconductor substrate to a predetermined depth below said second surface such that, after said implanting, said semiconductor substrate comprises:
• a first portion immediately adjacent to said first surface and comprising, in said first concentration, said dopant;
• and
• a second portion extending vertically from said predetermined depth to said second surface and comprising, in a second concentration higher than said first concentration, one of said dopant and a combination of said dopant and said different dopant such that said second portion has said given conductivity type at a higher conductivity level than said first portion;
• and,
• forming a device layer on said insulator layer, said device layer comprising multiple semiconductor devices and said first portion and said second portion of said semiconductor substrate each extending laterally and continuously so as to traverse below each of said multiple semiconductor devices.

A method of forming a semiconductor structure comprises:

• forming a semiconductor substrate having a first surface and a second surface opposite said first surface;
• forming an insulator layer on and immediately adjacent to said second surface;
• performing additional processing so as to form in said semiconductor substrate:
• a first portion immediately adjacent to said first surface and comprising, in a first concentration, a dopant having a given conductivity type such that said first portion has said given conductivity type;
• and
• a second portion extending vertically from said first portion to said second surface and comprising said dopant in a second concentration greater than said first concentration such that said second portion has said given conductivity type at a higher conductivity level than said first portion;
• and,
• forming a device layer on said insulator layer, said device layer comprising multiple semiconductor devices and said first portion and said second portion of said semiconductor substrate each extending laterally and continuously so as to traverse below each of said multiple semiconductor devices.