Vertical gate LDMOS device

A method of fabricating a vertical gate region in a laterally diffused metal oxide semiconductor (LDMOS) transistor, the method comprising:

• depositing a first masking layer on an n-well region implanted on a substrate;
• patterning the first masking layer to define an area;
• depositing a second masking layer over the area;
• etching through the second masking layer in a first portion of the area to expose the n-well region;
• etching the exposed n-well region to form a first trench such that the first trench extends from a surface of the n-well region to a first depth in the n-well region;
• filling the first trench by a first gate material;
• etching through the second masking layer in a second portion of the area to expose at least a portion of the n-well region
• depositing a third masking layer over the area;
• etching through a first portion of the third masking layer to expose a portion of the first gate material;
• removing the first gate material from the exposed portion to form a second trench that extends from the surface of the n-well region to a second depth that is greater than the first depth;
• and
• filling the second trench with a second gate material to form an asymmetric gate of the LDMOS transistor.