Semiconductor memory device and manufacturing method thereof

A semiconductor device comprising:

• a first conductive layer;
• a second conductive layer;
• a first insulating layer in contact with a side surface of the first conductive layer and a side surface of the second conductive layer;
• a third conductive layer between the first conductive layer and the second conductive layer with the first insulating layer interposed between the third conductive layer and each of the first conductive layer and the second conductive layer;
• a second insulating layer over the third conductive layer;
• an oxide semiconductor layer over the first conductive layer, the second conductive layer, and the second insulating layer, wherein the oxide semiconductor layer is electrically connected to the first conductive layer and the second conductive layer;
• a third insulating layer over the oxide semiconductor layer;
• and
• a fourth conductive layer over the third conductive layer with the second insulating layer, the oxide semiconductor layer, and the third insulating layer interposed therebetween,
• wherein the second insulating layer is provided between the first conductive layer and the second conductive layer with the first insulating layer interposed between the second insulating layer and each of the first conductive layer and the second conductive layer.

A semiconductor device comprising;

• a first semiconductor layer;
• a first insulating layer over the first semiconductor layer, wherein the first insulating layer includes an opening reaching the first semiconductor layer;
• a first conductive layer over the first semiconductor layer and in the opening of the first insulating layer;
• a second conductive layer over the first semiconductor layer with the first insulating layer interposed therebetween;
• a second insulating layer over the first insulating layer and in contact with a side surface of the first conductive layer and a side surface of the second conductive layer;
• a third conductive layer over the second insulating layer and between the first conductive layer and the second conductive layer with the second insulating layer interposed between the third conductive layer and each of the first conductive layer and the second conductive layer;
• a third insulating layer over the third conductive layer;
• a second semiconductor layer over the first conductive layer, the second conductive layer, and the third insulating layer, wherein the second semiconductor layer is an oxide semiconductor layer and electrically connected to the first conductive layer and the second conductive layer;
• a fourth insulating layer over the second semiconductor layer;
• a fourth conductive layer over the third conductive layer with the third insulating layer, the second semiconductor layer, and the fourth insulating layer interposed therebetween;
• a fifth insulating layer over the second conductive layer and the fourth conductive layer;
• and
• a fifth conductive layer over the second conductive layer and adjacent to a side surface of the fourth conductive layer with the fifth insulating layer interposed therebetween,
• wherein the third insulating layer is provided between the first conductive layer and the second conductive layer with the second insulating layer interposed between the third insulating layer and each of the first conductive layer and the second conductive layer.