Implant for performance enhancement of selected transistors in an integrated circuit

A method for forming a semiconductor structure, the method comprising:

• performing a first implant into a semiconductor substrate to form a well in which a plurality of transistors of a same conductivity type will be formed, wherein each transistor of a first subset of the plurality of transistors to be formed has a transistor width less than a predetermined width and each transistor of a second subset of the plurality of transistors to be formed has a transistor width not less than the predetermined width, and wherein the first subset and the second subset are mutually exclusive;
• forming a patterned masking layer over the semiconductor substrate and the well, wherein the patterned masking layer exposes locations of the semiconductor substrate in the well in which transistors of the first subset of the plurality of transistors will be formed and does not expose locations of the semiconductor substrate in the well in which transistors of the second subset of the plurality of transistors will be formed;
• performing a second implant into the semiconductor substrate using the patterned masking layer such that the second implant enters the semiconductor substrate at the locations exposed by the patterned masking layer;
• removing the patterned masking layer;
• and
• forming the plurality of transistors in the well, wherein a channel region of each transistor of the first subset of the plurality of transistors is formed in a portion of the semiconductor substrate which received the second implant and a channel region of each transistor of the second subset of the plurality of transistors is formed in a portion of the semiconductor substrate which did not receive the second implant.

A method for forming a semiconductor structure, the method comprising:

• performing a first implant into a semiconductor substrate to form a well in which a plurality of transistors of a same conductivity type will be formed, wherein each transistor of a first subset of the plurality of transistors to be formed has a transistor width that satisfies a predetermined width constraint and each transistor of a second subset of the plurality of transistors to be formed has a transistor width that does not satisfy the predetermined width constraint, and wherein the first subset and the second subset are mutually exclusive;
• performing a second implant into the semiconductor substrate such that the second implant enters the semiconductor substrate at locations in the well in which transistors of the first subset of the plurality of transistors will be formed and does not enter the semiconductor substrate at locations in the well in which transistors of the second subset of the plurality of transistors will be formed;
• and
• forming the plurality of transistors in the well, wherein a channel region of each transistor of the first subset of the plurality of transistors is formed in a portion of the semiconductor substrate which received the second implant and a channel region of each transistor of the second subset of the plurality of transistors is formed in a portion of the semiconductor substrate which did not receive the second implant,
• wherein forming the plurality of transistors in the well is further characterized in that each transistor of the first subset of the plurality of transistors has a transistor width which satisfies the predetermined width constraint by being less than a predetermined transistor width and each transistor of the second subset of the plurality of transistors has a transistor width which does not satisfy the predetermined width constraint by not being less than the predetermined transistor width.