Dual-leadframe multi-chip package and method of manufacture
AssigneeAlpha and Omega Semiconductor Incorporated
InventorsKai Liu, Lei Shi, Jun Lu, Anup Bhalla
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AssigneeAlpha and Omega Semiconductor Incorporated
InventorsKai Liu, Lei Shi, Jun Lu, Anup Bhalla
Estimating the term…
A dual-leadframe multi-chip package comprises a first leadframe with a first die pad, and a second leadframe with a second die pad; a first chip mounted on the first die pad functioning as a high-side MOSFET and second chip mounted on the second die pad functioning as a low-side MOSFET. The package may further comprises a bypass capacity configured as a third chip mounted on the first die pad or integrated with the first chip. The package may further comprise a three-dimensional connecting plate formed as an integrated structure as the second die pad for electrically connecting a top contact area of the first chip to a bottom contact area of the second chip. A top connecting plate connects a top contact area of the second chip and a top contact area of the third chip to an outer pin of the first leadframe.
A method for manufacturing a dual-leadframe multi-chip package, comprises the following steps:
A method for manufacturing a dual-leadframe multi-chip package, comprises the following steps:
Dependencies are inferred from the claim text.