Semiconductor strain gauge array

A process for lithographically fabricating a strain monitoring system comprising an array of semiconductor strain cells, said process comprising:

• A) a step of lithographically fabricating an array of strain gages on a silicon on insulator wafer having a buried oxide layer, each strain gage in the array comprising:
• i) a 4-resistor bridge adapted to provide an electrical signal corresponding to the strain in the bridge,
• ii) at least two multiplexers adapted to provide addressability to the 4-resistor bridge,
• utilizing the following steps:
• i) a set of doping steps comprising doping portions of the wafer with a p-type dopant and an n-type dopant, utilizing masks to create 4-leg bridges and thin film transistors in the substrate,
• ii) a set of isolation steps comprising the deposition of an insulating oxide layer over the p and n doped substrate to isolate the 4-leg bridges from the multiplexers and the sensor cells from each other,
• iii) one of more opening steps comprising etching the insulating oxide layer with masks to produce openings for electrical contacts,
• iv) a set of metallization steps comprising the utilization of masks with the deposition of a plurality of metal layers separated by interlayer dielectrics to provide the electrical contacts to the 4-leg bridges and the multiplexers,
• B) a step of transferring the array of strain gages to a polyimide film, and
• C) steps of providing electrical controls and data acquisition components separate from the array of semiconductor strain cells.