Wafer-level packaging mechanisms
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsJing-Cheng Lin, Jui-Pin Hung
Life of this patent
Estimating the term…
Abstract
The embodiments of mechanisms of wafer-level packaging (WLP) described above utilize a planarization stop layer to determine an end-point of the removal of excess molding compound prior to formation of redistribution lines (RDLs). Such mechanisms of WLP are used to implement fan-out and multi-chip packaging. The mechanisms are also usable to manufacture a package including chips (or dies) with different types of external connections. For example, a die with pre-formed bumps can be packaged with a die without pre-formed bumps.
Claims20
A method of forming a semiconductor package, comprising:
- providing a carrier with an adhesive layer disposed thereon;
- providing a die comprising a substrate, wherein a plurality of bond pads are formed over the substrate, and wherein a planarization stop layer is formed over the plurality of bond pads;
- placing the die on the adhesive layer;
- forming a molding compound to cover the die, wherein the molding compound surrounds the die;
- planarizing the molding compound until the planarization stop layer is exposed;
- removing an entirety of the planarization stop layer;
- and
- forming redistribution lines over the die, wherein the redistribution lines electrically connect to the at least one of the plurality of bond pads.
A method of forming a semiconductor package, comprising:
- providing a carrier with an adhesive layer disposed thereon;
- providing a first die comprising a first substrate, wherein a plurality of first bond pads are formed over the substrate, and wherein a planarization stop layer is formed over the plurality of first bond pads;
- placing the first die on the adhesive layer;
- providing a second die comprising a second substrate;
- placing the second die on the adhesive layer;
- forming a molding compound to cover the first die and the second die, wherein the molding compound surrounds the first die and the second die;
- planarizing the molding compound until the planarization stop layer is exposed;
- removing an entirety of the planarization stop layer;
- and
- forming redistribution lines over the first die and the second die, wherein the redistribution lines electrically connect to the at least one of the plurality of first bond pads and at least one of the plurality of second bond pads.
A method of forming a semiconductor package, comprising:
- placing a die on a carrier using an adhesive layer, wherein the die comprises a substrate having a plurality of conductive pads over a surface of the substrate and a planarization stop layer over the plurality of conductive pads;
- testing the die prior to placing the die on the carrier;
- forming a molding compound to cover the die, wherein the molding compound surrounds the die;
- exposing the planarization stop layer;
- and
- removing the planarization stop layer.
Dependencies are inferred from the claim text.