US 8,667,370 B1Granted

Systems and methods for arbitrating use of processor memory

AssigneeMarvell Internationa Ltd.

InventorsPantas Sutardja, Hong-Yi Chen

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Abstract

A system including a processor, a FIFO, and an arbiter module. The processor includes a processor core and a memory. The processor core processes data stored in a memory and executes instructions using the memory. The FIFO receives streaming data and outputs the streaming data to the memory. The arbiter module, in response to the FIFO not being filled to a predetermined threshold, allows the processor core to access the memory at a higher priority than the FIFO to permit the processor core to process data including any streaming data stored in the memory, and to execute instructions using the memory. The arbiter module, in response to the FIFO being filled to the predetermined threshold, allows the FIFO to access the memory at the higher priority than the processor core to permit the FIFO to output the streaming data, without having the FIFO overflow, to the memory.

Claims14

Dependent claims

A system, comprising:

a processor, wherein the processor includes
a processor core;
a memory in communication with the processor core,
wherein the processor core is configured to (i) process data stored in the memory, and (ii) execute instructions using the memory;
a first-in first-out buffer configured to (i) receive streaming data, and (ii) output the streaming data to the memory for processing by the processor core;
and
an arbiter module configured to
in response to the first-in first-out buffer not being filled to a predetermined threshold with the streaming data, allow the processor core to access the memory at a higher priority than the first-in first-out buffer to permit the processor core to (i) process data stored in the memory including any streaming data output to the memory by the first-in-first-out buffer, and (ii) execute instructions using the memory;
and
in response to the first-in first-out buffer being filled to the predetermined threshold with the streaming data, allow the first-in first-out buffer to access the memory at the higher priority than the processor core to permit the first-in-first-out buffer to output the streaming data, without having the first-in first-out buffer overflow, to the memory for processing by the processor core.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/785,803Filed 5 Mar 2013 · continuation
Priority: 10 Apr 2007
Granted: 4 Mar 2014
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

G11C 29/00
Checking stores for correct operation
G11B 20/18
Digital recording or reproducing: error detection or correction; Testing , e.g. of drop-outs
G11B 2220/657
Said memory being attached to the recording medium: memory in disc [MID]
G11C 2029/0411
Detection or location of defective memory elements , e.g. cell constructio details, timing of test signals: online error correction

Family

Application60/910,959Us provisional application · filed 10 Apr 2007
Application11/789,605Parent of this division · filed 25 Apr 2007
Application13/465,964Parent of this continuation · filed 7 May 2012
US 8,176,386 B1Parent of this division · filed 8 May 2012
US 8,392,799 B1Parent of this continuation · filed 5 Mar 2013
Application13/465,964Parent of this division
US 8,667,370 B1This patent

From the US filing history. Foreign family members aren’t listed.