US 8,665,928 B1Granted

Circuit for generating an output clock signal synchronized to an input clock signal

AssigneeXilinx, Inc.

InventorsMatthew H. Klein, David F. Taylor

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Abstract

A circuit generates an output clock signal synchronized to an input clock signal. The circuit includes a reference clock port, a phase interpolator, and a phase controller. The reference clock port receives a reference clock signal. The phase interpolator generates the output clock signal that, as a function of a variable control value, is an interpolation between two reference phases. The reference phases are generated from the reference clock signal and have a reference frequency. The phase controller generates the variable control value providing a phase rotation rate. An output frequency of the output clock signal equals a sum of the reference frequency and the phase rotation rate. The output frequency matches an input frequency of the input clock signal.

Claims15

Dependent claims

A circuit for generating an output clock signal synchronized to an input clock signal, comprising:

a reference clock port configured to receive a reference clock signal;
a crystal oscillator coupled to the reference clock port and configured to generate the reference clock signal, the reference clock signal having a fixed crystal frequency;
a phase-locked loop coupled to the reference clock port and configured to generate, from the reference clock signal, at least one reference phase having the reference frequency, and align a first division of the reference clock signal by a first integer and a second division of the at least one reference phase by a second integer;
wherein the phase-locked loop is further configured to align the first and second divisions at a synchronization frequency that nominally equals the fixed crystal frequency divided by the first integer and the reference frequency divided by the second integer;
a phase interpolator coupled to the reference clock port and configured to generate the output clock signal that, as a function of a variable control value, is an interpolation between two of a plurality of reference phases;
wherein the plurality of reference phases are generated from the at least one reference phase and from the reference clock signal and have a reference frequency;
and
a phase controller coupled to the phase interpolator and configured to generate the variable control value providing a phase rotation rate,
wherein an output frequency of the output clock signal equals a sum of the reference frequency and the phase rotation rate;
and
wherein the output frequency matches an input frequency of the input clock signal.

8 more elements

A circuit for clock synchronization, comprising:

a reference clock port configured to receive a reference clock signal, wherein the reference clock signal has a first reference frequency, and the first reference frequency divided by a first integer equals a second reference frequency divided by a second integer;
and
a plurality of clock synchronization circuits for generating a plurality of respective output clock signals synchronized to a plurality of respective input clock signals, wherein each clock synchronization circuit includes:
a phase interpolator coupled to the reference clock port and configured to generate the output clock signal that, as a function of a variable control value, is an interpolation between two of a plurality of reference phases;
wherein the plurality of reference phases are generated from the reference clock signal and have the second reference frequency;
and
a phase controller coupled to the phase interpolator and configured to generate the variable control value providing a phase rotation rate,
wherein an output frequency of the respective output clock signal equals a sum of the second reference frequency and the phase rotation rate, and the output frequency matches an input frequency of the respective input clock signal.

5 more elements

A data repeater circuit, comprising:

a data receiver configured to recover an input clock signal and a serial sequence of data bits received from a first communication link;
a reference clock port configured to receive a reference clock signal;
a phase interpolator coupled to the reference clock port and configured to generate an output clock signal that, as a function of a variable control value, is an interpolation between two of a plurality of reference phases, wherein the plurality of reference phases are generated from the reference clock signal and have a reference frequency;
wherein an output jitter of the output clock signal is less than an input jitter of the input clock signal, the output jitter includes a reference jitter of the reference clock signal and a quantization jitter of the phase interpolator, and the quantization jitter is an inverse of the reference frequency divided by a product of a number of the plurality of reference phases and a number of weighted combinations for the interpolation between the two of the plurality of reference phases;
a phase controller coupled to the data receiver and the phase interpolator, the phase controller configured to generate the variable control value providing a phase rotation rate, wherein an output frequency of the output clock signal equals a sum of the reference frequency and the phase rotation rate, and the output frequency matches an input frequency of the input clock signal;
and
a data transmitter coupled to the data receiver and the phase interpolator, the data transmitter being configured to transmit the serial sequence of data bits on a second communication link, the data transmitter further being configured to transmit the serial sequence of data bits synchronized to the output clock signal.

4 more elements

Dependencies are inferred from the claim text.