Spare cell insertion based on reachable state analysis
AssigneeInternational Business Machines Corporation
InventorsManikandan Viswanath, Samuel I. Ward
Life of this patent
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Abstract
Spare cells are inserted in a region of an integrated circuit design based on a logic complexity of the region. The logic complexity can be computed based on the number of reachable states of digital logic in the region, and can be correlated to a desired spare cell insertion rate which is then compared to the actual spare cell utilization in the region. The target spare cell rate can further based on logic complexity values for neighboring regions with a proximity penalty.
Claims12
A method of placing spare cells in an integrated circuit design comprising:
- receiving a description of the integrated circuit design which includes a plurality of cells interconnected to form a plurality of nets, by executing first program instructions in a computer system;
- identifying at least one region of the integrated circuit design having digital logic, by executing second program instructions in the computer system;
- computing a logic complexity value for the region based on the number of reachable logic states of the digital logic in the region, by executing third program instructions in the computer system;
- and
- inserting a number of spare cells in the region based on the logic complexity value, by executing fourth program instructions in the computer system.
A computer system comprising:
- one or more processors which process program instructions;
- a memory device connected to said one or more processors;
- and
- program instructions residing in said memory device for placing spare cells in an integrated circuit design by receiving a description of the integrated circuit design which includes a plurality of cells interconnected to form a plurality of nets, identifying at least one region of the integrated circuit design having digital logic, computing a logic complexity value for the region based on the number of reachable logic states of the digital logic in the region, and inserting a number of spare cells in the region based on the logic complexity value.
A computer program product comprising:
- a computer-readable storage medium;
- and
- program instructions residing in said storage medium for placing spare cells in an integrated circuit design by receiving a description of the integrated circuit design which includes a plurality of cells interconnected to form a plurality of nets, identifying at least one region of the integrated circuit design having digital logic, computing a logic complexity value for the region based on the number of reachable logic states of the digital logic in the region, and inserting a number of spare cells in the region based on the logic complexity value.
Dependencies are inferred from the claim text.