Method for reducing latency in a solid-state memory system while maintaining data integrity

A method of reducing latency in read operations from a plurality of solid-state storage devices arranged in N solid-state storage channels, where N is a number greater than 4, the method comprising the steps of:

• a. providing a central control system for queuing commands for said N solid-state storage channels;
• b. providing each solid-state storage channel with a buffer storage and a control system for controlling operation of a corresponding solid-state storage device, said control system being operable to receive a multiplicity of queued commands from said central control system and reorder an execution of said commands to minimize a latency of said corresponding solid-state storage device;
• c. providing a parity engine coupled to said N solid-state storage channels, said parity engine utilizing data from at least two of said N solid-state storage channels to provide a fault tolerance for a loss of valid data from at least any two of said N solid-state storage channels;
• d. sending read commands to said N solid-state channels, each read command being sent to all of the N solid-state channels simultaneously;
• e. performing a read operation of each read command from all of said solid-state storage channels to provide requested data;
• f. identifying said read operation has completed on N−1 of said solid-state storage channels;
• g. determining integrity of data read from said N−1 solid-state storage channels;
• h. if said data read from said N−1 solid state storage channels is valid, reconstructing data of a solid-state storage channel not having completed said read operation and transferring said requested data to a processor requesting said requested data, and if said data read from said N−1 solid-state storage channels is invalid, waiting for all solid-state storage channels to complete said read operation and determining integrity of data read from all said N solid-state storage channels;
• i. reconstructing data of any one solid-state storage channel found to be invalid from said determination of integrity of said data read from all said N solid-state storage channels;
• and
• j. repeating said steps (d)-(i) responsive to data from more than one solid-state storage channel being found to be invalid to correct for soft data errors.

A method of reducing latency in read operations from an array of solid-state storage devices arranged in N solid-state storage channels, where N is a number greater than 3, the method comprising the steps of:

• a. providing at least two of said N solid-state storage channels for storage of parity data;
• b. sending read commands to said N solid-state storage channels, each read command being sent to all of the N solid-state storage channels simultaneously;
• c. performing a read operation for each read command from all of said N solid-state storage channels to provide requested data;
• d. identifying said read operation has completed on N−1 of said solid-state storage channels;
• e. determining integrity of data read from said N−1 solid-state storage channels;
• f. if said data read from said N−1 solid-state storage channels is valid, reconstructing data of a solid-state storage channel not having completed said read operation and transferring said requested data to a processor requesting said requested data, and if said data read from said N−1 solid-state storage channels is invalid, waiting for all solid-state storage channels to complete said read operation, and determining if said data read from all said N solid-state channels is valid;
• g. reconstructing data of any one solid-state storage channel found to be invalid from said determination of integrity of said data read from all said N solid-state storage channels;
• and
• h. repeating said steps (b)-(g) responsive to data from more than one solid-state storage channel being found to be invalid to correct for soft data errors.