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US 8,658,499 B2Granted
Three dimensional NAND device and method of charge trap layer separation and floating gate formation in the NAND device
AssigneeSanDisk Technologies LLC
InventorsRaghuveer S. Makala, Johann Alsmeier, Yao-Sheng Lee
Life of this patent
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Abstract
A monolithic three dimensional NAND string includes a vertical semiconductor channel and a plurality of control gate electrodes in different device levels. The string also includes a blocking dielectric layer, a charge storage region and a tunnel dielectric. A first control gate electrode is separated from a second control gate electrode by an air gap located between the major surfaces of the first and second control gate electrodes and/or the charge storage region includes silicide nanoparticles embedded in a charge storage dielectric.
Claims20
A method of making a device, comprising:
- forming a stack of alternating layers of a first material and a second material over a substrate, wherein the first material comprises a conductive or semiconductor control gate material and wherein the second material comprises a first sacrificial material;
- etching the stack to form an opening in the stack;
- selectively removing the second material through the opening to form recesses;
- forming a blocking dielectric layer in the recesses to partially fill the recesses, the blocking dielectric layer located on surfaces of the control gate material;
- forming a charge storage material layer over the blocking dielectric such that the charge storage material layer partially fills the recesses and is located over the blocking dielectric layer;
- filling the recesses with a second sacrificial material;
- at least partially filling the opening with a third sacrificial material, such that the third sacrificial material contacts the second sacrificial material;
- reacting the second and third sacrificial materials to form a sacrificial compound material comprising the second and third sacrificial materials where the second and third sacrificial material layers contact each other;
- selectively removing the sacrificial compound material and any second sacrificial material remaining in the recesses while leaving unreacted portions of the third sacrificial material located adjacent to vertical edges of the control gate material;
- selectively removing portions of the charge storage material layer located in the recesses that are not covered by the unreacted portion of third sacrificial material located over the vertical edges of the control gate material, thereby forming vertically separated charge storage segments over the vertical edges of the control gate material.
7 more elements
A method of making a vertical, monolithic three dimensional NAND string, comprising:
- forming a stack of alternating layers of a first material and a second material over a substrate, wherein the first material comprises a conductive or semiconductor control gate material;
- etching the stack to form an opening in the stack;
- forming a blocking dielectric layer in the opening, the blocking dielectric layer located on surfaces of the control gate material;
- forming a charge storage region comprising metal silicide nanoparticles embedded in a charge storage dielectric matrix in the opening over the blocking dielectric layer;
- forming a tunnel dielectric layer in the opening;
- forming a semiconductor channel layer in the opening over the tunnel dielectric layer;
- and
- selectively removing the second material through the opening to form recesses before the step of forming the blocking dielectric such that the blocking dielectric and the charge storage region extend into the recesses.
5 more elements
A method of making a vertical, monolithic three dimensional NAND string, comprising:
- forming a stack of alternating layers of a first material and a second material over a substrate, wherein the first material comprises a conductive or semiconductor control gate material;
- etching the stack to form an opening in the stack;
- forming a blocking dielectric layer in the opening, the blocking dielectric layer located on surfaces of the control gate material;
- forming a charge storage region comprising metal silicide nanoparticles embedded in a charge storage dielectric matrix in the opening over the blocking dielectric layer;
- forming a tunnel dielectric layer in the opening;
- and
- forming a semiconductor channel layer in the opening over the tunnel dielectric layer;
- wherein the step of forming the charge storage region comprises:
- forming a silicon nitride containing layer comprising:
- (i) a silicon-rich silicon nitride layer, or (ii) a silicon sublayer over a silicon nitride sublayer;
- forming metal islands over the silicon nitride containing layer;
- reacting the metal islands with silicon in the silicon nitride containing layer to form the metal silicide nanoparticles;
- and
- forming a silicon nitride layer over the metal silicide nanoparticles to form the composite film comprising the metal silicide nanoparticles embedded in the charge storage dielectric matrix.
11 more elements
Dependencies are inferred from the claim text.