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US 8,650,429 B1Granted
Clock phase alignment
AssigneeXilinx, Inc.
InventorsGreg W. Starr, Xiang Zhu
Life of this patent
Estimating the term…
Abstract
A method and apparatus for clock phase alignment are described. An external clock is aligned to an internal clock by adjusting phase of the external clock. The external clock is of a physical medium attachment clock domain, and the internal clock is of a physical coding clock domain. After the aligning of the external clock to the internal clock, the external clock is maintained. The internal clock is aligned to the external clock by adjusting phase of the internal clock.
Claims20
A method for clock phase alignment, comprising:
- aligning an external clock to an internal clock by adjusting phase of the external clock using a first circuitry loop in a first alignment mode;
- wherein the external clock is of a physical medium attachment clock domain;
- wherein the internal clock is of a physical coding clock domain;
- after the aligning of the external clock to the internal clock, maintaining the external clock;
- and
- after the aligning of the external clock to the internal clock, aligning the internal clock to the external clock by adjusting phase of the internal clock using a second circuitry loop in a second alignment mode,
- wherein the first circuitry loop is activated during the first alignment mode and deactivated during the second alignment mode, and wherein the second circuitry loop is activated during the second alignment mode and deactivated during the first alignment mode.
4 more elements
An apparatus for clock phase alignment, comprising:
- a first circuitry loop configured to align a first clock signal in a physical medium attachment clock domain to a second clock signal in a physical coding clock domain by adjusting phase of the first clock signal in a first alignment mode;
- and
- a second circuitry loop coupled to the first circuitry loop;
- wherein the second circuitry loop is configured to align the second clock signal to the first clock signal by adjusting phase of the second clock signal, after the first clock signal is aligned to the second clock signal in a second alignment mode, and
- wherein the first circuitry loop is activated during the first alignment mode and deactivated during the second alignment mode, and wherein the second circuitry loop is activated during the second alignment mode and deactivated during the first alignment mode.
2 more elements
Dependencies are inferred from the claim text.