Local sense amplifier circuit and semiconductor memory device including the same
AssigneeSamsung Electronics Co., Ltd.
InventorsIn-Woo Jun, Won-Chang Jung
Life of this patent
Estimating the term…
Abstract
A local sense amplifier circuit in a semiconductor memory device, the local sense amplifier circuit including a local data sensing unit configured to amplify a voltage difference between a local input/output (I/O) line pair based on a local sensing enable signal to provide the amplified voltage difference to a global I/O line pair, the local I/O line pair including a first local I/O line and a second local I/O line, and a local I/O line control unit including a first capacitor and a second capacitor, the first capacitor increasing a voltage level of the first local I/O line based on the local sensing enable signal, the second capacitor increasing a voltage level of the second local I/O line based on the local sensing enable signal.
Claims16
A local sense amplifier circuit in a semiconductor memory device, the local sense amplifier circuit comprising:
- a local data sensing unit configured to amplify a voltage difference between a local input/output (I/O) line pair based on a local sensing enable signal to provide the amplified voltage difference to a global I/O line pair, the local I/O line pair including a first local I/O line and a second local I/O line;
- and
- a local I/O line control unit including a first capacitor and a second capacitor, the first capacitor increasing a voltage level of the first local I/O line based on the local sensing enable signal, the second capacitor increasing a voltage level of the second local I/O line based on the local sensing enable signal,
- wherein the first capacitor is a first metal oxide semiconductor (MOS) transistor that includes a gate electrode connected to the first local I/O line, a first electrode receiving the local sensing enable signal, and a second electrode connected to the first electrode of the first MOS transistor, and
- wherein the second capacitor is a second MOS transistor that includes a gate electrode connected to the second local I/O line, a first electrode receiving the local sensing enable signal, and a second electrode connected to the first electrode of the second MOS transistor.
A local sense amplifier circuit, in a semiconductor memory device, the local sense amplifier circuit comprising:
- a local data sensing unit configured to amplify a voltage difference between a local input/output (I/O) line pair based on a local sensing enable signal to provide the amplified voltage difference to a global I/O line pair, the local I/O line pair including a first local I/O line and a second local I/O line;
- and
- a local I/O line control unit including a first capacitor and a second capacitor, the first capacitor increasing a voltage level of the first local I/O line based on the local sensing enable signal, the second capacitor increasing a voltage level of the second local I/O line based on the local sensing enable signal, wherein the first capacitor is a first MOS transistor that includes a gate electrode receiving the local sensing enable signal, a first electrode connected to the first local I/O line, and a second electrode connected to the first electrode of the first MOS transistor, and wherein the second capacitor is a second MOS transistor that includes a gate electrode receiving the local sensing enable signal, a first electrode connected to the second local I/O line, and a second electrode connected to the first electrode of the second MOS transistor.
A semiconductor memory device, comprising:
- a memory cell array connected to a bitline pair;
- a bitline sense amplifier circuit configured to amplify a voltage difference between the bitline pair based on a bitline sensing enable signal;
- a column selection circuit configured to provide the amplified voltage difference between the bitline pair to a local input/output (I/O) line pair in response to a column selection signal, the local I/O line pair including a first local I/O line and a second local I/O line;
- a local sense amplifier circuit including a first capacitor and a second capacitor, and configured to amplify a voltage difference between the local I/O line pair based on a local sensing enable signal to provide the amplified voltage difference between the local I/O line pair to a global I/O line pair, the first capacitor increasing a voltage level of the first local I/O line based on the local sensing enable signal, the second capacitor increasing a voltage level of the second local I/O line based on the local sensing enable signal;
- and
- an I/O sense amplifier circuit configured to amplify a voltage difference between the global I/O line pair to generate a sensing output signal.
An electronic device, comprising:
- a processor;
- a memory cell array coupled to the processor, the memory cell array including at least one memory cell connected to a bitline pair;
- a bitline sense amplifier circuit configured to receive voltages of the bitline pair and provide amplified voltages to a local input/output (I/O) line pair, the local I/O line pair including a first local I/O line and a second local I/O line;
- a local sense amplifier circuit including a first capacitor and a second capacitor, the local sense amplifier circuit being configured to amplify a voltage difference between the local I/O line pair based on a local sensing enable signal to provide the amplified voltage difference between the local I/O line pair to a global I/O line pair, the first capacitor increasing a voltage level of the first local I/O line based on the local sensing enable signal, the second capacitor increasing a voltage level of the second local I/O line based on the local sensing enable signal;
- and
- an I/O sense amplifier circuit configured to amplify a voltage difference between the global I/O line pair to generate a sensing output signal.
Dependencies are inferred from the claim text.